K-micro announces availability of CatsEye Development systems

    New single and dual cores offer expanded options for CPU subsystem designers and greatly reduce time-to-market

San Jose, Calif. – March 10, 2009 – K-micro (Kawasaki Microelectronics), a leader in advanced ASICs, announced the availability of development systems for the MIPS32® 24Kf processors to speed up the hardware and software development time associated with complex ASIC designs..

The CatsEye Development system includes all the functions needed to make a complete CPU subsystem for a variety of applications ranging from internet equipment such as routers and gateways, to entertainment devices such as media players and servers. The development system enables K-micro customers to do concurrent hardware and software designs and verify functionality before committing to the final ASIC chip. This approach results in a much shorter development time because all the core functions have already been developed, tested, and proven to interoperate together. Equally important is the reduced time to production since the software was developed and debugged concurrently with the hardware. The development systems’ OCP interface offers the flexibility to add specific functionality to the designs so each customer can add their own “secret sauce” to the chip and verify the operation quickly.

“Our customers will be able to develop advanced ASICs in a fraction of the time normally associated with development programs of this magnitude, saving anywhere from 6-12 months on a typical development program that normally ranges for 12-24 months,” said Joel Silverman, vice president of marketing at K-micro. “Advanced tools enable our customers to rapidly add, remove or replace any of the IP with their own or a third party IP.”

The development system contains a board with a CatsEye chip mounted on it, along with a variety of interfaces such as memory controller, Flash memory controller, 2 Gb Ethernets, OCP interfaces used to add other IP to the design, 3 UARTS, a PCI Express device, as well as many GPIO pins that can be used to generate additional interfaces. K-micro customers can use the CatsEye development system during the design phase of their ASICs or rent the boards if they will need them for an extended time period.

The CatsEye chip is an advanced SoC that contains a complete CPU subsystem with two MIPS 24Kf cores, two 10/100/1000 Mbit Ethernet MACs, security processor, memory controllers and host of other peripherals that are required for SoC developments. The CatsEye chip is the starting point, and customers can readily add, remove or replace any of the components to make the chip that they need.

About K-micro (Kawasaki Microelectronics)

K-micro’s innovative ASIC technologies and world-class design support are used in the consumer electronics, computer, office-automation, networking and storage markets. The company is an active participant in industry standards organizations, including InterNational Committee for Information Technology Standards (INCITS) Technical Committee T10 for SCSI Storage Interfaces, Optical Internetworking Forum (OIF), PCI Special Interest Group (PCI-SIG), USB Implementers Forum, Digital Living Network Alliance (DLNA), Universal Plug and Play Forum (UPnP), the Digital Display Working Group (DDWG), Home Phoneline Networking Alliance (HomePNA), Multimedia over Coax Alliance (MoCA), and OCP International Partnership (OCP-IP). K-micro has design centers in San Jose, Taipei, and Tokyo. For more information, contact the company at 408-570-0555, or visit http://www.k-micro.us


Sacha Arts
Slider & Associates
Tel.: +1 408-356-3099
E-mail: Email Contact

Review Article Be the first to review this article
Featured Video
More Editorial  
ASIC Design Engineer for Ambarella at Santa Clara, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Verification Engineer for Ambarella at Santa Clara, CA
Test Development Engineer(Job Number: 17001697) for Global Foundaries at Santa Clara, CA
Senior FPGA Designer for Fidus Electronic Product Development at Fremont, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy