Low Cost, Low Power SPI4.2 Cores Bolstered With Enhanced Buffer Management Features
HILLSBORO, OR NOVEMBER 19, 2008 -- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that its industry-leading LatticeSCM™ FPGA family-based SPI4.2 MACO™ (“Masked Array for Cost Optimization”) cores have been enhanced by adding sophisticated link layer buffer management options. Compared to competitive FPGAs, the LatticeSCM FPGA family has offered the industry’s most feature-rich SPI4.2-based cores and bridge reference designs at the lowest cost, power and printed circuit board footprint. These new features enhance this solution portfolio by allowing designers the option to use a parameterizable buffer manager for applications needing per-channel bandwidth management.
“We continue to enhance our SPI4.2 solution portfolio by integrating sophisticated system-level features, while maintaining the low cost and power targets that have made Lattice a leading SPI4.2 programmable gasket solution provider,” said Shakeel Peera, Director of Strategic Marketing for SRAM FPGAs. “Designers working on 10G Carrier Ethernet and Packet over SONET platforms will find these features useful as they architect systems designed around determinism and Service Level Agreement (SLA) guarantees.”
The LatticeSCM FPGA platform provides designers with multiple hardened SPI4.2 cores using Lattice’s exclusive MACO structured ASIC technology. MACO technology delivers pre-engineered, standard-compliant IP functions, developed by Lattice, that shorten end-system time to market and dramatically lower device cost, power and PCB footprint targets. These new features provide designers with a programmable buffer manager capable of:
- Up to 16 separate physical FIFOs per TX/RX direction
- Packet over-flow and error drop
- Both store & forward as well as cut-through operation
- Parameterizable buffer depth and thresholds
- Dynamic channel provisioning
- Programmable sequencer-based scheduler
Further information can be found at:
http://www.latticesemi.com/products/fpga/sc/macoonchipstructuredasicb/scmspi4.2core.cfm A XAUI to SPI4.2 bridge solution can found at:
About the LatticeSC and LatticeSCM FPGA Families
The Extreme Performance LatticeSC™ FPGA family provides the unsurpassed performance and connectivity that is essential for high-speed applications. Fabricated on Fujitsu’s 90nm CMOS process technology utilizing 300mm wafers, LatticeSC FPGAs are packed with features that accelerate chip-to-chip, chip-to-memory, high-speed serial, backplane and network data path connectivity.
Integrated into the LatticeSC devices are high-channel count SERDES blocks supporting 3.8Gbps data rates, PURESPEED parallel I/O providing industry-leading 2Gbps speed, innovative clock management structures, FPGA logic operating at 500MHz and massive amounts of block RAM. Lattice’s unique Masked Array for Cost Optimization (MACO) embedded structured ASIC blocks are available on the LatticeSCM devices, delivering pre-engineered, standard-compliant IP functions such as high-speed Memory Controllers, SPI4.2, Ethernet MACs and PCI Express control functions developed by Lattice to shorten end-system time to market.
About Lattice Semiconductor
Lattice is the source for innovative FPGA, CPLD and Mixed Signal programmable logic solutions. For more information, visit www.latticesemi.com
Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our third party software suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company’s Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.