Unique 3-D Tomographic Approach from Cornell and SRC Detects Smallest Defects, Decreases Development Time, Eliminates Circuit Failures, Advances Next-Generation Nodes

RESEARCH TRIANGLE PARK, N.C.—(BUSINESS WIRE)—September 16, 2008— As transistors and the wires that connect them continually shrink to make computer chips more powerful, defects in the device nanostructures become more difficult to detect. Semiconductor Research Corporation (SRC), the worlds leading university-research consortium for semiconductors and related technologies, today joined with Cornell University to announce successful demonstration of a unique electron tomography approach that provides vital three-dimensional information. Helping to resolve the show-stopping defect problems associated with next generations of chips, this new solution should enable cost-effective fabrication of future technology nodes.

Accurate and effective imaging of defects, with the associated reliability challenges confronting chipmakers, has always been a key component of the chip development process. To overcome this challenge, SRC is funding research into new ways to see into the detailed workings of integrated circuits. The new tomographic analysis technique employed by Cornells researchers allows for an unprecedented degree of high-resolution imaging in all three dimensions of the device down to ~2nm ( http://people.ccmr.cornell.edu/~davidm/Muller_tomography.html).

Traditional thinking says a picture is worth a thousand words. But in the business of building integrated circuits, a picture can be worth 10 million dollars, or even more, if it gives you information that decreases development time or eliminates failures in your latest entry in the race to be first with a next-generation integrated circuit, said Dr. Steve Hillenius, executive vice president of SRC-GRC, an SRC entity dedicated to extending the future of CMOS. This new tomographic approach from Cornell will help the industry not only to continue Moores Law, but to do it affordably.

Cornells electron tomography method is implemented with equipment found in most metrology labs, allowing for widespread adoption by industries that rely on understanding the chemical and physical features of nanoscale structures. Also, it borrows reconstruction algorithms and analysis routines from both the biological and medical imaging fields, such that mature commercial software and hardware central to three-dimensional analysis already exists. The use of such readily available tools as a starting point will make this three-dimensional imaging technique easily accessible to existing laboratories.

A major defect in just one of these transistors can ruin the entire chip, and manufacturers obviously want to minimize this occurrence. Devices are so small, however, that finding and analyzing these defects is equivalent to searching an area the size of the U.S. for a needle in a haystack, said Dr. David Muller, associate professor of applied and engineering physics and a research project leader at Cornell. Our research allows the IC builders to measure tiny devices to make sure they meet the required specifications used by the IC architects.

In addition, while smaller transistors allow for greater capabilities to be squeezed onto a chip, they also dictate fabrication of more interconnecting wires that are equally shrunk. Small wires, less than 100nm wide, don't carry electricity as effectively as larger wires used in previous technology nodes. The increased electrical resistance in the smaller wires leads to wasted power through heat generation, along with other undesirable effects.

The Cornell teams three-dimensional imaging technique allows for the cross-section of a copper wire to be measured within each 2nm slice of the reconstruction, yielding measurements at many points along the wire for a proper average. This allows a more accurate prediction of the wires performance, such as heat generation, during normal operation in a computer chip.

Backed by investment from SRC and IBM, the Cornell team designed the novel incoherent bright field (IBF) tomographic imaging technique for a traditional scanning transmission electron microscope (STEM) to produce images without distortions from thick, dense materials commonly used in semiconductor devices. When used in conjunction with electron tomography, the IBF imaging technique has a predicted resolution limit of ~2nm, even in relatively thick sections of materials. This method is useful for cases where traditional methods fail, and has been proven by reconstruction and analysis of a complete copper wire/barrier layer structure.

Per its charter, SRC will continue to take a lead role in collaborating on enhancements brought about by academic research associated with semiconductor design and manufacturing.


Global Research Collaboration (GRC) is one of three research program entities of SRC. Celebrating 26 years of collaborative research for the semiconductor industry, SRC defines industry needs, invests in and manages the research that gives its members a competitive advantage in the dynamic global marketplace. Awarded the National Medal of Technology, Americas highest recognition for contributions to technology, SRC expands the industry knowledge base and attracts premier students to help innovate and transfer semiconductor technology to the commercial industry. For more information, visit www.src.org.

NOTE TO EDITORS: In the Internet address noted in this news release, there is a tilde before davidm. This symbol may not appear properly in some systems.

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