"This is a huge opportunity for the industry as optimal placement of circuits in the design process will deliver scaling of semiconductors that is independent of feature size, providing Moore's Law progress at less cost than other options," said Professor Jason Cong, chair of the UCLA Computer Sciences Department (www.ucla.edu). "Closing such a large optimality gap will be equivalent to several technology generation advancements. In comparison, the introduction of copper interconnects was equivalent to a 30% interconnect length reduction, and so is each generation of device scaling, but each requires a multi-billion dollar investment."
For the past 40 years, transistor and interconnect scaling has been the required solution for maintaining continuous incremental improvements to semiconductors. With the state-of-art chip features now down to 45nm, scaling is limited by both physical and economic challenges. For most companies, fabrication factories become too expensive beyond the 30nm process, although feature sizes are projected to shrink several more generations below that.
"We're running out of gas when forced to count on traditional performance gains. The implications of new software that can give us the equivalent of one technology node in die size and cost savings is great progress," said Dr. William Joyner, director of CAD and Test Sciences at SRC. "UCLA research has demonstrated such possibility, even on a very well studied and classical problem such as circuit placement. The UCLA team's persistence has paid off by proving there's room for robust gains independent of further scaling."
Focusing on benefits derived from reduction in wire length gap during research begun in 2003, Cong and the UCLA team demonstrated significant 'optimality gaps' among even the best available circuit placement algorithms at that time. The gaps ranged from 70 to as much as 150 percent away from the optimal solutions, in terms of the total interconnect length. (http://cadlab.cs.ucla.edu/~pubbench) Closing such a large optimality gap is equivalent to several technology generation advancements. Reflecting today's news, SRC funded a circuit placement tool at UCLA which thus far has demonstrated capability of 30 percent improvement, equivalent to one technology generation. Further progress is expected.
To achieve this gain, there are two techniques: (1) a multi-level or multi-scale sequence of steps to iteratively reduce the problem complexity and then project the solution of a coarser problem to that of a finer problem until a solution to the original problem is obtained, and (2) application of sophisticated, constrained non-linear optimization at each step. Success of the techniques resulted from close collaboration among research in computer science and mathematics by Professor Cong and Professor Tony Chan, leader of UCLA's applied mathematics group. (http://cadlab.cs.ucla.edu/cpmo/)
Highlights of the circuit placement tool and method are documented in a book published this month, titled "Modern Circuit Placement - Best Practices and Results," edited by Cong and Dr. Gi-Joon Nam of IBM Austin Research Laboratory.
"This technique improvement is like laying out a new city that is much more efficient while still maintaining minimum setbacks," said Dale Edwards, program manager at SRC.
"The success of this research demonstrates how collaboration between CAD and mathematics can produce results that far outperform the state of the art," said Dr. Sankar Basu, NSF program director and a joint sponsor of the research (www.nsf.gov). "We hope this example will inspire more CAD researchers to cross boundaries and seek interdisciplinary collaborations."
As chipmakers gain from their use of such design tools and technologies, consumers ultimately will benefit from the higher levels of integration and performance improvements without the historical costs associated with the continuing shrinkage of chips. Per its charter, SRC will continue to take a lead role in collaborating on enhancements brought about by academic research in efficient algorithms, tools and processes associated with semiconductor design and manufacturing.
Global Research Collaboration (GRC) is one of three research program entities of SRC. Celebrating 25 years of collaborative research for the semiconductor industry, SRC defines industry needs, invests in and manages the research that gives its members a competitive advantage in the dynamic global marketplace. Awarded the National Medal of Technology, America's highest recognition for contributions to technology, SRC expands the industry knowledge base and attracts premier students to help innovate and transfer semiconductor technology to the commercial industry. Based in Research Triangle Park, NC, SRC's GRC program drives long-term semiconductor research contracts on behalf of its participating members: Advanced Micro Devices, Inc., Applied Materials, Inc., Axcelis Technologies, Inc., Cadence Design Systems, Freescale Semiconductor, Inc., Hewlett-Packard Co., IBM Corp., Intel Corp., LSI Corp., Mentor Graphics Corp., The MITRE Corp., Novellus Systems, Inc., Rohm and Haas Electronic Materials, Texas Instruments Inc. and Tokyo Electron Ltd. SRC also seeks to leverage funding from global government agencies. For more information, visit www.src.org.
SRC (Cardinal Communications)
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