The problem, of course, is even more complex than simply drawing a smaller line. When the power is turned on, these devices also have to operate exactly as planned. At very small geometries, timing and power are critical: for example, a single 45nm transistor can turn on and off in the time it takes light to travel less than a tenth of an inch, and in a typical device, millions of transistors are firing at once.
In fact, over these distances and at these speeds, the very concept of "at once" really has no meaning. Tiny physical and electrical variations can cause delays that sideline even the best chip designs, potentially causing millions of chips to fail. To avoid this, said Cadence executives, designers need to be sure -- at the design stage -- that the chip will be successful after manufacturing. Since much of the manufacturing-side knowledge is still out of the designers' hands, this requires sweeping improvements to the software that designers use.
"Fundamentally, what is at stake is the quality of electronic products today," said Mike Fister, President and CEO of Cadence Design Systems. "The electronics industry simply cannot afford to find problems in manufacturing. The best place for fast, efficient, cost-effective correction, analysis, repair and optimization is at the designer's desk. If the chip is correct by design, there should be few unexpected problems once it is manufactured; What you design is what you will get."
This requires an improved ability to predict how a design's physical and electrical characteristics evolve during manufacturing. The sooner a designer can achieve a high level of predictability, the better the design quality. Historically, a small industry of 'design for manufacturing' software startups have attempted to satisfy this emerging need. However, what designers are increasingly asking for is an holistic set of solutions that are fully integrated throughout the digital and custom design environments. This is critical to enabling fast, accurate design and manufacturing of innovative electronic products.
"If this were a matter of just solving a single problem, you could do it with a single software program at any time in the design stage. But design for manufacturing addresses a much bigger set of challenges," said Mike McAweeney, vice president of DFM for Cadence. "Integrating these capabilities into the design flow allows designers of all types of chips to make choices and solve problems that we didn't even think of when the integration effort began. This sort of activity creates its own momentum and synergy."
"TSMC is pleased to work with Cadence to create and qualify interoperability between the foundry's DFM data sets for advanced technology and the EDA tools and models that designers use," said Kuo Wu, deputy director of design service marketing of Taiwan Semiconductor Manufacturing Company. "We've had extensive collaboration with Cadence and its partners on this effort, and our mutual customers have already benefited from the results."
At the event, Cadence also unveiled broad improvements to its Encounter design environment, providing digital chip designers with a much higher degree of certainty that the design will function correctly after manufacturing.
"Semiconductor design is becoming increasingly expensive, so designers want to get their projects done quickly and correctly," said Jim Feldhan, analyst at Semico Research. "Engineers targeting 65nm and 45nm technologies are encountering significant design challenges, but time to market constraints means they can't spend a lot more time solving them. That means the design tools have to manage key manufacturing dependencies for them. In other words, the Cadences of the world have to embed solutions to problems, such as leakage power, design rule complexity and process variation, into their products. That's the challenge that Cadence faces, and it's doing remarkably well."
Cadence unveiled these developments at its annual CDNLive! Silicon Valley Conference today at the San Jose Convention Center. The three-day conference is attended by hundreds of world's leading semiconductor designers from companies such as NEC, Freescale Semiconductor, Qualcomm, IBM and ST Microelectronics, to name a few, many of whom share their own breakthroughs in technical presentations and seminars on design techniques.
"CDNLive! Silicon Valley is a user event, driven by-and-for the design community," said Cadence CTO Ted Vucurevich. "It is focused on sharing ideas that solve today's most pressing semiconductor engineering challenges. It's as important to the semiconductor design industry as a leading medical conference is to doctors and the medical community at large."
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Cadence is a registered trademark and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact: Dan Holden Cadence Public Relations (408) 944-7457 Email Contact