Comprehensive System-Level Verification Framework Eliminates Bottleneck for Complex SoCs
Adaptive Verification IP combines the time-to-market advantages of automated verification with the quality of in-context, knowledge-based verification that was previously only possible manually. Adaptive Verification IP complements existing random or directed-random methods with a powerful new approach to reducing overall verification time, improving verification confidence, and enabling the explosion in SoC size and complexity to continue.
"To be successful in the market, tomorrow's complex consumer devices must run multiple applications simultaneously, which requires fast and efficient on-chip communication," said Jonathan Morris, general manager of the System Design Division at ARM. "To minimize risk, designers need a complete toolbox, including on-chip communication and verification IP, plus a tools framework that enables them to configure, analyze and verify their complex SoC devices."
"On-chip communication represents a significant challenge in SoC designs at 90 nanometers and beyond," said Christian Heidarson, senior research analyst, Gartner. "The market for on-chip interconnect and memory controller IP today stands at about $46 million* but if delivered through a system-level design tools that successfully automates the task of optimizing the flow of data between functions on the chip, this market has the potential to grow four fold over the next five years."(1)
As the design cycle increasingly begins at the system level, so must verification. For high-level modeling, Adaptive Verification IP can be licensed as an add-on to the RealView SoC Designer tool, which provides a system-level framework that architects of today's most complex SoCs use to create, explore and optimize platforms long before the hardware and software teams begin their work.
Adaptive Verification IP is written C++ and encapsulated in System Verilog for RTL compatibility. To provide a detailed verification of system functionality and performance, Adaptive Verification IP can also be licensed standalone for use within all popular verification tool flows from the leading EDA vendors.
Mentor Graphics is the first major EDA vendor to ensure that Adaptive Verification IP functions smoothly within its verification methodology.
"We've been working closely with ARM to integrate the new Adaptive Verification IP into Questa and our Advanced Verification Methodology (AVM)," said Robert Hum, vice president and general manager of Mentor Graphics Design Verification and Test Division. "Our Questa second generation verification platform is specifically designed to address the verification needs of today's extremely complex SoC devices, for which the de facto interconnect specification is AMBA. This combined solution will give customers greatly improved verification productivity and the confidence that they have met their system functionality and performance goals."
AMBA Adaptive Verification IP will be available to lead Partners in Q3 2007 and generally available in Q4 2007.
ARM designs the technology that lies at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM's comprehensive product offering includes 16/32-bit RISC microprocessors, data engines, graphics processors, digital libraries, embedded memories, peripherals, software and development tools, as well as analog functions and high-speed connectivity products. Combined with the company's broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. More information on ARM is available at http://www.arm.com.
(1). Gartner, Inc., "Market Share: Semiconductor Intellectual Property, Worldwide, 2005" by Christian Heidarson and Jim Tully, July 24, 2006
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