Will Strauss of Forward Concepts said, "Intrinsity has shown its mettle with the Titan core. No other 32-bit PowerPC core even comes close to the 2.0 GHz 4000-plus DMIPS performance of this core. Fast14 technology really is fast."
Intrinsity's CEO, Bob Russo, explained, "Ordinary static synthesized, or even firm, implementations of similar PowerPC cores struggle to attain 600 MHz. Using Fast14 logic, our designers got over three times more speed from Titan -- over 2 GHz -- using the same 90 nm process technology. Titan's 4000-plus DMIPS at under 2.5 Watts power dissipation is unprecedented, as is the very small area envelope.
"Titan defines the power of our Fast14 technology and the excellence of our design team -- performance characteristics comparable to a full-custom implementation with a fraction of the resources, and at a faction of the cost," Russo concluded.
The Titan FastCore is the first in series of ultra-high performance processor cores that Intrinsity is developing by applying its Fast14 Technology to industry-standard processor architectures. The Titan FastCore is an ISA FastCore based on the PowerPC instruction set architecture, and is designed to maximize the speed, power and area advantages provided by Fast14 technology. ISA FastCores deliver multicore-level performance using a single core -- typically 3x or greater than that of conventional static implementations.
IMS' Embedded Processing Analyst Tom Hackenberg said, "As the return on investment of shrinking design processes diminishes, SoC solutions providers are under pressure to find alternative ways to increase microprocessor performance, reduce power dissipation or reduce area; Intrinsity's design of Titan seems an innovative response to all these issues."
Intrinsity is also developing, RTL FastCores, based on register transfer level representations of popular embedded IP cores. RTL FastCores are cycle-accurate, exact replacements of standard cores. Using the same CMOS process, RTL FastCores typically have twice the performance of conventional synthesized static implementations, while maintaining similar MHz/mW characteristics. The cycle accuracy of RTL FastCores allows them to employ the same software and test infrastructure used with original embedded processor built with conventional static logic.
Targeted at high-speed networking and control plane applications, the Titan FastCore is based on the Book-E Enhanced PowerPC Architecture with a 64-bit IEEE floating point unit (FPU) and features a dual symmetric dispatch, superscalar, pipelined processing unit, along with memory management, cache control, timers and debug facilities often required by embedded products. Separate level zero and one instruction and data caches are provided. The L1 caches use the MESI protocol and are snooped to maintain memory coherency in multicore applications. The processor connects to local on-chip peripherals through a memory-coherent, high performance bus. Intrinsity also developed Titan's high-speed memories, leveraging the performance of Fast14 to sustain the high circuit speeds required.
Fast14 Domino Logic Increases Speed and Reduces Area
Intrinsity's Fast14 1-of-N domino logic (NDL) increases the Titan core's clock speed by a) employing faster dynamic logic, b) using a smaller number of more complex gates, c) reducing the overall transistor count and d) performing logic work exclusively with smaller, faster n-channel (NMOS) devices. The omission of the p-channel devices in the logic path reduces both the circuit size and its parasitic capacitance. In addition, Fast14 logic signals are represented in a 1-of-N encoding style, rather than binary, reducing signal encode and decode requirements and further minimizing both the size and power consumption of the circuit.
Because the logic evaluation direction is through the NMOS network, ("n-stack") to ground, individual transistors can automatically be sized to speed up the evaluation operation. This also allows designers to create more complex functions in a single gate than is possible using conventional CMOS static logic design styles, reducing the number of stages needed to implement a logic function.
Multi-phase overlapping clocking ensures low risk, manufacturable dynamic logic
Historically, the use of dynamic logic has been limited because it requires overly precise manipulation of the clock delays to prevent timing problems. Signal delay variability due to load and parasitics has also been a common problem with traditional dynamic logic styles.
The Fast14 technology used in the Titan FastCore solves the timing issue by using multiphase overlapping clocks with a nominal 50% duty cycle that eliminates the need for synchronizing latches or registers at the cycle boundaries. Critical paths such as arithmetic units, control logic or SRAM interfaces can cross system clock cycle boundaries as needed without incurring the penalty of a register delay. The Titan core has very few registers or latches in the timing critical logic paths, thereby conserving time and silicon area. The multiphase clocks in Titan increase the circuit's tolerance for moderate amounts of clock uncertainty due to duty cycle error, clock-period jitter, or clock skew, and allow time borrowing between gates. Hold time problems and race conditions are virtually eliminated, also enabling painless integration of dynamic and static logic elements in the Fast14 design environment.
Low noise and low power
Traditional dynamic logic does not provide an inversion function, so both true and complement values of a bit must be generated and transmitted, resulting in a logic style referred to as dual-rail dynamic logic. One of the wires representing a bit must switch every cycle, whether the data changes or not, leading to reduced power efficiency and increased circuit noise. In contrast, Fast14 as used in Titan employs 1-of-N signal encoding, where the radix N can typically be between one and eight. 1-of-N signal encoding uses a single signal net to represent a bit, effectively reducing the switching factor by 1/2 or more. Lower switching factors, combined with the inherent shielding provided by surrounding quiescent signals, results in both lower power consumption and less noise. Increased wiring complexity is mitigated by a bundle routing, and noise coupling is further reduced by altering signal ordering upon layer changes and automatic opportunistic shielding.
1-of-N signal encoding, when applied to the inputs of an NDL gate, results in a high fraction of the NMOS transistors being in the off state. Consequently, when the network evaluates, less electrical charge is discharged to ground, improving gate speed, power, and area efficiency.
Automated Design Methodology
Intrinsity's proprietary Fast14 Design Automation Platform was used to address Fast14 NDL-specific features in Titan, while industry-standard tools were used wherever possible for tasks such as formal verification, timing analysis and scan pattern generation. This flow provides an efficient, reliable, repeatable methodology that results in highly efficient and manufacturable designs.
Intrinsity, Inc. is a design technology company that provides the designs, tools, technologies, and expertise so its customers can efficiently and predictably produce high performance, low-power and cost-effective products. Intrinsity's proprietary Fast14 technology is used to create FastCore embedded cores, which provide not only circuit speeds of up to and beyond 3 GHz, but also the means to trade-off speed, power and area to achieve the optimal solution to customer design targets. Fast14 technology includes a combination of process specific libraries, a specification language and a set of tools that help automate the design flow. Intrinsity's corporate headquarters are located in Austin, Texas. For further information regarding Intrinsity, please visit our web site at http://www.intrinsity.com.
Contacts: Nancy B. Green The William Baldwin Group +1 650.856.6192 Email Contact Mike Gehl Intrinsity +1 970.949.6480 Email Contact