STARC to Develop Low-Power "PRIDE" Reference Flow Using Common Power Format

SAN JOSE, CA -- (MARKET WIRE) -- May 21, 2007 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced that Japan's Semiconductor Technology Academic Research Center (STARC) has selected Si2's Common Power Format (CPF) in the development of STARC's Low Power "PRIDE" reference design flow v1.5. STARC is targeting this low-power flow, for release to its member companies in October 2007, using technologies from the Cadence Logic Design Team Solution as well as the Cadence advanced-verification and digital-implementation solutions.

STARC recently completed a feasibility study and validated a CPF-based low-power flow using a test design. STARC engineers performed physical prototyping confirming significant benefits of CPF-based low-power design flow when tested against a non-CPF flow. STARC expects their member companies to realize 50 percent reduction in turn-around time, early low-power architectural explorations and greater design reusability.

CPF is a design specification language that addresses the limitation in traditional design-automation-tool flows by capturing the designer's intent for power management and by enabling the automation of advanced power-lowering design techniques. By preserving low-power design intent throughout the design, the solution eliminates laborious manual work, reduces power-related chip failure and provides power predictability early in the design process. CPF v1.0 is available as a Si2 standard to the industry at large.

"STARC is responding to increasing requests from our member companies for an advanced low-power solution," said Nobuyuki Nishiguchi, vice president and general manager of STARC. "Our low-power flow using CPF will not only provide a fully integrated design, verification and implementation methodology, but also offers a new environment for low-power architectural exploration in the early design stages and reduced turn-around time."

"Selection of the Common Power Format by STARC to enable their new low-power flow is a strong reflection of the maturity, use model, and adoption of CPF as a practical power format within the design community," said Jan Willis, senior vice president, Industry Alliances at Cadence. "STARC's leadership in developing an integrated methodology will enable their member companies to deliver low-power products in volume and will enhance the productivity of a broad base of designers."

The Semiconductor Technology Academic Research Center, STARC, is a research consortium co-founded by major Japanese semiconductor companies in December 1995. STARC's mission is to contribute to the growth of the Japanese semiconductor industry by developing leading-edge, system-on-chip (SoC) design technologies.

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

Cadence is a registered trademark, and the Cadence logo is a trademark, of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

For more information, please contact:
Michael Fournell
Cadence Design Systems, Inc.
Direct: 408-428-5135

Email Contact

Review Article Be the first to review this article

Synopsys: Custom Compiler

Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Upcoming Events
Preparing for the Cognitive Era: Education, Occupation and You at SJSU Student Union Theater 211 South 9th Street San Jose CA - Oct 18, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
15th IEEE/ACM ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
CST: Webinar series

Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise