New ASIC line addresses need for low power and high bandwidth
"The initial success of this DTV application substantiates our vote of confidence in TSMC's 90nm eDRAM process; a success we plan to replicate on other applicable designs," said Kyoichi Kissei, executive VP and member of the board at K-micro.
"K-micro's adoption of the TSMC 90nm eDRAM process for DTV application signifies a milestone in our technology development, manifesting that we have successfully overcome historic eDRAM process difficulties such as pass gate leakage, cell capacitance, and stacked contact without compromising cost effectiveness," said Dr. Kenneth Kin, senior VP of world wide sales and service at TSMC. "K-micro's production exemplifies the win-win synergy that is the hallmark of our customer partnerships."
TSMC's 90nm eDRAM requires fewer processing steps than competitive processes while delivering competitively-sized macro specifications and process stability. The process has been in production since the first quarter of 2006.
The 90nm embedded DRAM process is CMOS logic-based and incorporates an add-on memory module. The embedded process eliminates I/O power consumed interfacing with external DRAM devices, provides a wider bus and lowers material cost. The process consumes less active and standby power than SRAM and features a 60% smaller macro size. The process is ideal for system-on-chip (SoC) platforms for high-bandwidth applications such as digital TV and game consoles and for low-power applications such as handheld and miniature consumer electronics.
K-micro's innovative ASIC technologies and world-class design support are used in the consumer electronics, computer, office-automation, networking and storage markets. The company is an active participant in industry standards organizations, including InterNational Committee for Information Technology Standards (INCITS) Technical Committee T10 for SCSI Storage Interfaces, Optical Internetworking Forum (OIF), PCI Special Interest Group (PCI-SIG), USB Implementers Forum, Universal Plug and Play Forum (UPnP), the Digital Display Working Group (DDWG), Home Phoneline Networking Alliance (HomePNA), Multimedia over Coax Alliance (MoCA), and OCP International Partnership (OCP-IP). K-micro has design centers in San Jose, Taipei, and Tokyo. For more information, contact the company at 408-570-0555, or visit http://www.k-micro.us /.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company's total managed capacity in 2006 exceeded seven million (8-inch equivalent) wafers, including capacity from two advanced 12-inch GigaFabs, four eight-inch fabs, one six-inch fab, as well as TSMC's wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.