-- Prototyping: TSMC's prototyping programs streamline the transition from first silicon to production, including the QuickStart(SM) IP program, the Prototype Diagnostics Alliance and CyberShuttle(SM). CyberShuttle allows multiple customers to share the costs of a single mask set and prototype wafers on a pilot run.
-- Extensive libraries and IP: TSMC's 45nm design ecosystem includes the industry's most advanced technology libraries, including standard cell, standard I/O, single-port SRAM, dual-port SRAM and more. The Library Alliance Program supports TSMC's extensive portfolio of silicon-proven third-party IP.
-- Process design kit (PDK) quality assurance: TSMC 45nm PDKs cover the entire design flow from schematic entry, simulation, layout, and layout check to post-simulation. The 6-stage automatic PDK quality assurance flow with over 133 procedures ensures consistent quality control and faster development lead time. Adoption is simplified with smart installation and tutorial, and design accuracy is improved with support for well proximity effect (WPE) modeling, Monte Carlo simulation, and estimated parasitic RC device information for pre-simulation.
-- Design for Manufacturability (DFM): TSMC's 45nm (DFM) initiative goes beyond traditionally supplied design rules and SPICE models, providing additional manufacturing variance data that is essential for achieving high yields at the nanometer level. A model-based approach and a rule-based approach are available for designer implementation, with a DFM Data Kit (DDK) for third-party EDA tools and a TSMC DFM toolkit with advisories and utilities.
TSMC also provides extensive in-house services that enable reliable, rapid tape-out and production, along with comprehensive backend services from CP test to drop-shipping.
Momentum Builds for 45nm
Interest in TSMC's 45nm process is high, as evidenced by broad participation in TSMC's 45nm CyberShuttle prototyping program. A double-digit number of companies are on board the 45nm CyberShuttle along with a host of IP vendors. One 45nm CyberShuttle has been successfully completed, while three more are scheduled for May, August and December.
"Our customers' enthusiasm for the 45nm CyberShuttle is an auspicious leading indicator of the success of TSMC's 45nm process," said Dr. Rick Tsai, president and CEO of TSMC. "We are marshalling the full resources of our design ecosystem to support our 45nm process and respond to the anticipated demand."
TSMC's 45nm Process
TSMC's 45nm process employs a combination of 193nm immersion photolithography and extreme low-k (ELK) material. With an exceptionally high gate density and high-density 6T SRAM cell, more than 500 million transistors will easily fit into a 70mm(2) die area. TSMC's Low Power (LP) 45nm process is expected to be available first, followed soon after by the General Purpose and High Performance (GS) process. In addition, the 45nm logic family includes a low-power triple gate oxide (LPG) option. All three processes offer multiple threshold voltage (Vt) core devices and 1.8V, 2.5V, 3.3V I/O options to meet different product requirements.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company's total managed capacity in 2006 exceeded seven million (8-inch equivalent) wafers, including capacity from two advanced 12-inch GigaFabs, four eight-inch fabs, one six-inch fab, as well as TSMC's wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see www.tsmc.com
Chuck Byers, 408-382-7919