International Conference on Computer Aided Design (ICCAD) Previews Novel "Designers' Perspectives" Technical Track

BOULDER, Colo.—(BUSINESS WIRE)—October 10, 2006— The International Conference on Computer Aided Design (ICCAD), the Electronic Design Automation (EDA) industry's top technical conference, is now previewing its "Designers' Perspectives" Technical Track, which will provide for the first time real designers' views and experience on critical topics in electronic design. The track, which will run Tues. Nov. 7 from 8:30 a.m.-6:30 p.m., is an integral part of the Conference which will be held November 5-9 at the DoubleTree Hotel in San Jose, California.

The Designers' Perspectives Track in ICCAD focuses on critical issues including Design for Robustness, Design for Analog, and Design for Verification.

Perspectives: Robustness and Reliability in Design

The first session highlights pressing problems in reliability from designers' perspectives. Marek Patyra from Intel, identifies two fundamental problems with popular methodologies for "Design for Reliability," and he offers some guidance in reaching reliability constraints. Fabian Klass from P.A. Semi, addresses the use of statistical methods in circuits and outlines some ideas on integrating these methods into CAD tools. Mondira (Mandy) Pant, from Intel, discusses chief challenges in designing a robust and reliable power grid. Noriyuki Ito, of Fujitsu Limited, presents the application of statistical timing analysis to microprocessor design and outlines unsolved related problems. Dennis Abts, from Cray Inc., provides examples of reliability features used in current Cray machines. The last speaker, back at ICCAD by popular demand, Phillip Restle of IBM Watson, highlights state-of-the-art techniques in designing robust clock distribution networks for both processors and ASIC designs.

Perspectives: Design to Enable Verification

Moderated by Anmol Mathur from Calypto Design Systems, this session focuses on various modeling and validation methodologies to minimize time, efforts, and money required to arrive at verification. Tor Jeremiassen, of TI, highlights the importance of using system modeling environments (ESL based) to validate system-level designs and individual IP blocks in a cohesive environment. Tse-Yu Yeh , from P.A. Semi, will describe the methodology and experience in designing a two-core SOC to support both simulation and emulation for verification. Pascal Urard, STMicroelectronics, discusses the use of verification techniques between system level and RTL. In addition, two Nvidia verification architects, Ira Chayut and David Whipp, focus respectively on the causes of non-determinism and mismatches between C and RTL models, and on grammars to define transaction structures and strategies that ESL designers use to minimize subsequent verification activity. Finally, Jason Stinson, from Intel, describes pre-silicon design and design for test measures that reduce the effort of post-silicon design and verification, including measures for IP blocks.

Perspectives: Mixed-signal Design Experiences

This session, moderated by Mar Hershenson from Sabio Labs, acknowledges the fast increase in mixed-signal chips that requires integration and an efficient and repetitive design methodology. Six top analog designers will give us their perspective on the current issues in analog CAD and design. Marwan Hassoun, from Keyeye Communications, presents the difficult process of choosing a process technology for mixed-signal ASICs. Arvin Shahani, from Fairchild, gives us an overview of the CAD requirements for mixed-signal design. Hamid Rategh, from Scintera, addresses the specific complexities of implementing programmable analog blocks. Jaeha Kim, of Rambus, discusses the idea of migrating digital formal verification methods to analog and the impact that it could have. George Powley, from Intel, highlights the benefits of using analog behavioral models and mixed-signal simulation to design high-speed serial links. Finally, Milton Ribeiro, of Impeva Labs, discusses how to use high-level description languages such as Verilog-AMS and VHDL-AMS, to create executable specifications for analog blocks.

According to Marek Patyra from Intel Corp., "It is gratifying to be part of this year special session on designers' perspective and to be able to exchange design ideas with other researchers and engineers."

Details for participating in this exciting, novel track can be examined in ICCAD's web site ( effective immediately.

Registration Details

For more information on registering for this year's conference, please visit


The International Conference on Computer Aided Design (ICCAD) has served EDA and Design professionals for the last 20 years by highlighting new challenges and innovative solutions for integrated circuit design technologies and systems. To learn more, please visit the ICCAD website at


ICCAD Publicity Chair
Juan-Antonio Carballo, 408-239-6130
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HighPointe Communications (for ICCAD)
Barbara Marker, 503-209-2323
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