"The POWR607 device provides ideal support for any 16-bit or 32-bit microprocessor-based system," said Stan Kopec, Lattice corporate vice president of marketing. "Designers traditionally have used a design-specific set of discrete off-the-shelf devices to generate the CPU Reset, Power Supply Fault Interrupts and Watchdog Timers for each microprocessor-based design. The POWR607 device can implement all these functions through logic programmed into its on-chip CPLD, which results in a standardized, lower cost design solution.
"The Power Manager II devices are programmable logic devices plus analog peripheral circuitry optimized for power management functions," said Kopec. "Because these devices are software programmable, each of the five family devices can replace any combination of supervisory devices, reset generator devices, hot-swap controllers, power supply sequencers and power supply trimming and margining circuits, as well as multiple resistors and capacitors. Consequently, a Power Manager II device reduces both the bill-of-material cost and the time to market."
The POWR607 device uses Lattice's award winning Power Manager architecture. The device can monitor up to 6 circuit board power supplies and generate signals such as a CPU Reset, including pulse stretching and power supply fault interrupt, using the on-chip 16 macrocell CPLD, four programmable timers and 7 outputs (two of which also can be configured as high voltage MOSFET drivers). The POWR607 device can be powered down using an external logic signal, or by an internally generated signal. Once in the power down state, the device draws a mere 10 microamperes from the power supply. The POWR607 devices are packaged in space-saving 5mm x 5mm QFN packages.
Due to its low cost, very small footprint and low power standby feature, the ispPAC-POWR607 is an ideal power management solution in handheld consumer, telecom and industrial applications.
All Power Manager devices, including the POWR1220AT8, POWR1014/A, POWR6AT6 and POWR607, provide a standard, off-the-shelf programmable mixed-signal solution for power management across multiple circuit boards. This solution improves reliability, speeds time-to-market and reduces cost.
Designs for the ispPAC-POWR607 are implemented using the Windows-based Lattice PAC-Designer® Software version 4.7.
PAC-Designer 4.7 software is available for download free of charge from the Lattice website, www.latticesemi.com
Pricing and Availability
In high volume (100KU+) the price of the ispPAC-POWR607 devices in the 32-pin QFN package and industrial temperature range is $0.95. Samples are available now.
About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry's broadest range of Programmable Logic Devices (PLD), including Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Devices (CPLD), Programmable Mixed-Signal Products (ispPAC®) and Programmable Digital Interconnect Devices (ispGDX®). Lattice also offers industry leading SERDES products.
Lattice continues to deliver "More of the Best" to its customers with comprehensive solutions for system design, including an unequaled portfolio of high performance, non-volatile and low cost FPGAs.
Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. For more information, visit http://www.latticesemi.com.
Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our third party silicon suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.
Lattice Semiconductor Corporation, Lattice (& design), L (& design), ispPAC, ispGDX, PAC-Designer and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.
GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.
EDITORIAL/READER CONTACT: Brian Kiernan Corporate Communications Manager Lattice Semiconductor Corporation 503-268-8739 voice 503-268-8193 fax Email Contact