The design of RF synthesizers remains one of the most challenging tasks in mobile RF systems because they must meet very stringent requirements of a low-cost, low-power and low-voltage monolithic implementation while meeting the phase noise and switching transient specifications. The work presented here is an outcome of a recent investigation conducted to develop a synthesizer architecture that exploits the strong advantages of deep-submicron digital CMOS process technology as well as advances in digital VLSI design.
The underlying theme of the techniques presented here is to maximize a digitally-intensive implementation by operating in a synchronous phase domain. The chief benefit obtained with this architecture is to allow the integration of the RF front-end with the digital back-end onto a single silicon die using a standard ASIC design methodology. The ideas developed here have been implemented in a commercial deep-submicron CMOS process and demonstrated on a working silicon chip in a Bluetooth transmitter for short-range communications and will soon be announced for a commercial single-chip GSM phone.
Key Topics Covered Include:
-- Digitally-Controlled Oscillator (DCO)
-- Normalized DCO
-- All-Digital Phase-Locked Loop (ADPLL)
-- Application: ADPLL-Based Transmitter
-- Behavioral Modeling and Simulation
-- Implementation and Experimental Results
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