"Our customers rely on Infineon for leading-edge and cost-effective chips to power the next generation of consumer, cellular and automotive products," said Mr. Christian Esser, Vice President Technology, Infineon Dresden. "PDF Solutions worked with our engineers to significantly accelerate our yield learning at 130nm and our engineers continue to benefit from the on-going use of PDF's methodology and tools for continuous yield optimization at that node. Our current 90nm project with PDF has shown further significant improvement in yield ramp speed. We chose to engage PDF Solutions because it offered us a comprehensive solution customized to our needs, delivered by a team of skilled engineers, and backed by a proven track record."
"Semiconductor companies face a growing challenge," said Dr. Andrzej Strojwas, Chief Technologist at PDF Solutions. "Shorter product life cycles require faster ramps but shrinking feature sizes and the introduction of new materials have led to a significant increase in ramp complexity." Added Dr. Strojwas, "Traditional yield improvement methods are losing their efficiency and result in sub-optimal allocation of ramp resources and budgets. PDF Solutions has spent the last 10 years developing and perfecting new methods and tools to support faster ramps. We are proud of our relationship with Infineon and are happy with their decision to continue to partner with PDF for their 90nm Logic node ramp."
The multiple stage 90nm project includes implementation of PDF Solutions' Compliance Level yield learning methodology, which focuses on increasing yields and reducing process variability. The 90nm CVi deployed in the Dresden fab is based on PDF Solutions' seventh generation short-flow test-chip technology and has been customized to Infineon's specific process conditions and product mix. Use of the CVi reduces the time and silicon budget required to identify, prioritize and resolve systematic and random yield detractors. The project also includes PDF Solutions' Printability Space Decomposition (PSD) methodology to identify, quantify and resolve yield loss caused by lithography, as well as PDF's Performance Variability CV(R) test chip (PV CV), a partial-field test chip that addresses transistor related yield loss due to manufacturing variability.
Additionally, Infineon is deploying PDF Solutions' advanced Scribe CV(R), which utilizes PDF's patented technology for densely packed test structures embedded on product wafers. PDF's Scribe CV provides 100x more information than traditional PCM structures and is used to improve yield excursion control during the mature, high volume production phase. Infineon also benefits from the integration of PDF Solutions' CVi to third party scanning electron microscopy (SEM) tools, enabling detection and fast localization of non-visual defects that are difficult to identify using standard inspection techniques.
About PDF Solutions
PDF Solutions, Inc. (Nasdaq: PDFS) is the leading provider of process-design integration technologies for manufacturing integrated circuits (ICs). PDF Solutions' software, methodologies and services enable semiconductor companies to create IC designs that can be more easily manufactured using manufacturing processes that are more capable. By simulating deep sub-micron product and process interactions, PDF Solutions offers clients reduced time to market, increased IC yield and performance, and enhanced product reliability and profitability. Headquartered in San Jose, Calif., PDF Solutions operates worldwide with additional offices in Europe and Japan. For more information, visit www.pdf.com.
PDF Solutions, Characterization Vehicle, and CV are registered trademarks of PDF Solutions, Inc. Other trademarks used herein are the property of their respective owners.
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