Serial RapidIO and VLYNQ Interfaces Pass Interoperability Testing for TI DSPs
"Collaboration with DSP ecosystem leaders such as TI is a cornerstone of our digital signal processing strategy and roadmap," said Omid Taheirna, general manager and vice president of the DSP division at Xilinx. "These new interfaces build on the co-processing platforms we delivered last year and pave the way for more synergistic solutions in the future"
"Our TI DSP solutions now have standardized high-speed interfaces to Xilinx FPGAs," said Joe Rigazio, DSP general manager for Worldwide Catalog and Emerging End Equipments at Texas Instruments. "Working together, TI & Xilinx reduce customer time-to-market for complex system designs in video client/infrastructure and digital communication markets."
Serial RapidIO Interoperability
The Serial RapidIO interface provides a very high speed connection between the FPGA and TI C6455 DSPs which enables high throughput for both data and clock. Xilinx RapidIO interface supports x1 and x4 lane Serial RapidIO links in both the Virtex-4 FX and Virtex-II Pro FPGA platforms. Both x1 and x4 lane configurations support operating link speeds of 1.25 Gbps, 2.5 Gbps, and 3.125 Gbps per lane. With the Xilinx Serial RapidIO interface designers can implement unique and flexible high performance architectures using TI DSPs in applications such as wireless and telecom infrastructures, digital video, and imaging.
VLYNQ is a serial low-pin count communications interface capable of operating up to 125 MHz. The new Xilinx VLYNQ interface provides a bridge to the CoreConnect On-chip Peripheral Bus (OPB) available on Xilinx FPGAs. With the Xilinx VLYNQ interface, designers can use TI TMS320DM6443 and TMS320DM6446 Davinci-based processors to communicate to custom-built or standard microprocessor peripherals such as such as extra UARTs and SPIs implemented on Spartan-3 and Spartan-3E FPGAs, providing a flexible and differentiated system solution to better meet changing market needs. The new VLYNQ interface follows the successful delivery of the EMIF interface and video-co processing kit for the DM642EVM by Xilinx. While designers can still communicate between Xilinx FPGAs and TI DSPs via the EMIF interface, they now have the choice to interface to FPGAs using VLYNQ and use the EMIF interface exclusively for interfacing TI DSPs to external memory, thus delivering higher system performance.
Pricing and Availability
The Xilinx VLYNQ interface is available now and priced at USD $995. The Serial RapidIO Physical Layer and Logical (IO) and Transport Layer Interface LogiCOREs are available from Xilinx today. The list price is $15,000 for the Physical Layer LogiCORE (DO-DI-RIO-PHY) and $10,000 for the Logical (IO) and Transport Layer Interface LogiCORE (DO-DI-RIO-LOG).Visit www.xilinx.com/dsp/coprocessing for more information on Xilinx co-processing solutions for TI DSPs.
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