William Ruby Appointed Vice President Marketing of EDA Power Reduction Company Golden Gate Technology

SAN JOSE, CA -- (MARKET WIRE) -- Aug 11, 2005 -- Golden Gate Technology Inc., specializing in nanometer IC power reduction, today announced that William Ruby has been appointed Vice President of Marketing for the company. Mr. Ruby was most recently a Director of Marketing at Cadence Design Systems. He reports to Dennis Heller, CEO.

"We are pleased to add Will to our executive staff," said Dennis Heller, Golden Gate CEO. "His understanding of the challenges faced by companies designing power-sensitive semiconductor products will help us continue to add more value to our offerings for power reduction."

"I am very excited to join the talented team at Golden Gate Technology," said William Ruby. "With its unique and proven technology, Golden Gate is able to automatically reduce power consumption while complementing traditional flows."

William Ruby brings over 12 years of low-power experience in the semiconductor and EDA industries to Golden Gate Technology. He has held senior marketing positions at Cadence, Synopsys/EPIC and Sequence, working on low power and mixed-signal software products. As an IC designer at Siemens, he was responsible for ultra-low power memory, analog, and digital design. Mr. Ruby has also served as a key member of the first Pentium microprocessor design team at Intel. He holds a BA in Physics from UC Berkeley, an M.S.E.E. from USC, and an M.B.A from San Jose State.

Importance of Power Reduction

Power reduction has become mission-critical for today's designs. Longer battery life, lower packaging costs, and higher reliability can all be achieved when power consumption is reduced. Many designs are limited in their performance and functionality due to excessive power consumption. A recent Gartner report even stated: "Keep in mind that power and programmability are the two major problems that have the potential to significantly slow Moore's law."(1)

About Golden Gate Technology

Golden Gate Technology, headquartered in San Jose, California, provides leading-edge tools for nanometer IC power reduction that work with existing design flows from major EDA vendors. Using WiresFirst™ technology, Golden Gate's power reduction software products -- Power Plan Gold™ and Power Optimize Gold™ can reduce chip power consumption by up to 25%. For more information please visit www.ggtcorp.com.

Golden Gate Technology, Inc. is headquartered at 1101 South Winchester Boulevard, Building P, San Jose, CA 95128, Phone: (408) 249-6200, Fax: (408) 249-6240. For sales inquiries, please email Email Contact. For general assistance e-mail: Email Contact

Notes to editors:

Photo available on request.

Power Plan Gold, Power Optimize Gold and WiresFirst are trademarks of Golden Gate Technology, Inc. All other trademarks and tradenames are the property of their respective holders.

(1) Gartner Research "What to See at DAC 2005" by Gary Smith. June 7, 2005.

Press Contact:
Georgia Marszalek
ValleyPR for Golden Gate
650 345 7477

Email Contact



Rating:


Review Article Be the first to review this article

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Fall Schedule: A Host of Must-attends
More Editorial  
Jobs
DDR 3-4-5 Developer with VIP for EDA Careers at San Jose, CA
Senior Methodology Automation Engineer for EDA Careers at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Proposal Support Coordinator for Keystone Aerial Surveys at Philadelphia, PA
Upcoming Events
11th International Conference on Verification and Evaluation of Computer and Communication Systems at 1455 DeMaisonneuve W. EV05.139 Montreal Quebec Canada - Aug 24 - 25, 2017
The Rise of Mechatronics at Dassault Systèmes San Diego 5005 Wateridge Vista Drive San Diego CA - Sep 12, 2017
The Rise of Mechatronics at Buca di Beppo - Pasadena 80 West Green Street Pasadena CA - Sep 13, 2017
DownStream: Solutions for Post Processing PCB Designs
S2C: FPGA Base prototyping- Download white paper
TrueCircuits: IoTPLL



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy