STATS ChipPAC Adds Package-on-Package (PoP) Solution to 3D Technology Portfolio

A Flexible Stacked Package Solution in a 1.4mm Footprint

SINGAPORE and UNITED STATES, April 6 /PRNewswire-FirstCall/ -- STATS ChipPAC Ltd. ("STATS ChipPAC" - Nasdaq: STTS and SGX: STATSChP), a leading independent semiconductor test and advanced packaging service provider, today announced that it has added Package-on-Package (PoP) to its three dimensional (3D) technology portfolio. 3D packages integrate devices vertically through stacking multiple die on a single substrate or multiple packages in a single solution to achieve higher functionality with a minimal increase in size and cost.

The increasing complexities of cell phones, PDAs, and other handheld products are driving the need for the maximum functionality in the smallest footprint, lowest profile, and lowest cost possible. While stacked die packages have been extremely successful in delivering increased functional integration in ultra thin profiles, cumulative yield impact and lack of Known Good Die (KGD) in some device applications necessitate pretesting of packaged devices in a 3D configuration. As a result, stacking pretested packages together in single solution is emerging as a next generation technology of choice in wireless applications.

For applications such as cell phones which require integration of a digital base band or digital signal processor (DSP) and an analog device, the strongest stacked package solutions are Package-in-Package (PiP) and Package-on-Package (PoP). PiP is a 3D package that stacks a fully tested Internal Stacking Module (ISM) on top of a Base Assembly Package (BAP) to form a single Chip Scale Package (CSP) solution. PoP is a 3D package in which fully tested packages such as single die FBGA or stacked die FBGA (typically memory die) are stacked on top of another single die FBGA or stacked die FBGA (typically base band or analog die) during the board mount process.

"We believe 3D packaging represents the next wave in package solutions to address the growing demand for increased silicon functional density in handheld products," said Scott Jewler, Chief Strategy Officer. "With our technology leadership in stacking up to seven die in a single package, our innovative Package-in-Package technology, and the addition of a Package-on-Package solution, STATS ChipPAC offers one of the most comprehensive 3D packaging portfolios in the industry today.

For customers who prefer to configure devices into the 3D package during the board mount process, PoP provides the greatest amount of flexibility in terms of mixing and matching IC technologies as well as procuring devices from multiple manufacturing sources."

The top package of a PoP is typically a single die Fine Pitch Ball Grid Array (FBGA) or stacked die FBGA with a package height less than 1.2mm. The bottom package of the PoP is a single die FBGA or stacked die FBGA package thinner than 1.0mm. Mounting the top package to bottom PoP package by means of peripheral solder balls produces a final stack up height as low as 1.4mm. Both packages are fully tested prior to being integrated into the 3D package and can be sourced from different device manufacturers, enabling semiconductor companies to customize their 3D package based on the application and the core competency of their suppliers.

To successfully integrate two packages into a 1.4mm solution, the bottom PoP package typically has a mold cap less than 0.27mm high to allow for the mounting of the top package without interference. This is achieved through an advanced transfer molding technology called Top Center Mold Gate (TCMG). TCMG requires a smaller clearance from the top die during the molding process, resulting in a thinner bottom package which is interconnected to the top package through peripheral solder balls.

"With STATS ChipPAC's leadership in advanced enabling technologies such as die thinning, film die attach, ultra low loop wire bonding, and mold technology, we provide some of the most complex 3D solutions available today," said Han Byung Joon, Chief Technology Officer of STATS ChipPAC. "PoP delivers increased functional integration in a small footprint with higher test yields and greater flexibility in mixed technologies."

PoP meets accepted package and board-level reliability standards of a CSP, including stringent drop shock test requirements for handheld devices, and is compliant to lead-free and "Green" materials sets based on JEDEC Moisture Sensitivity Level (MSL) 2A standard at 260 degrees centigrade reflow temperatures.

About STATS ChipPAC Ltd. (STATS ChipPAC)

STATS ChipPAC Ltd. is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions. A trusted partner and supplier to leading semiconductor companies worldwide, STATS ChipPAC's value proposition is total solutions of fully integrated, multi-site, end-to-end assembly and testing solutions that bring products to market and volume faster. Our customers are some of the largest wafer foundries, integrated device manufacturers (IDMs), as well as fabless companies in the United States, Europe and Asia. STATS ChipPAC is a leader in mixed signal testing and advanced packaging technology for semiconductors used in diverse end market applications including communications, power, digital consumer and computing. With advanced process technology capabilities and a global manufacturing presence spanning Singapore, South Korea, China, Malaysia, Taiwan and the United States, STATS ChipPAC has a reputation for providing dependable, high quality test and packaging solutions. The Company's customer support offices are centered in the United States (California's Silicon Valley, Arizona, Texas, Massachusetts, Florida, Colorado and North Carolina), with offices located in the Netherlands, United Kingdom, China, Singapore, Japan, Taiwan, South Korea and Malaysia. STATS ChipPAC's facilities include those of its subsidiary, Winstek Semiconductor Corporation in Hsinchu Valley, Taiwan. These facilities offer new product introduction support, pre- production wafer sort, final test, packaging and other high volume preparatory services. Together with our Research and Development Centers in Singapore, South Korea and test facilities in the United States, this forms a global network providing dedicated test engineering development and product engineering support for customers from design to volume production. STATS ChipPAC is listed on both the Nasdaq National Market and The Singapore Exchange. In addition, STATS ChipPAC is also listed on the Morgan Stanley Capital International (MSCI) Index and the Straits Times Industrial Index. Further information is available at

CONTACT: Singapore, Elaine Ang, Manager, Investor Relations / Corporate
Communications, +65-6824-7705, or fax, +65-6720-7826, or
Email Contact, or U.S., Drew Davies, Director, Investor
Relations, +1-408-586-0608, or fax, +1-408-586-0652, or
Email Contact, or Lisa Lavin, Marcom Manager, +1-208-939 3104,
or fax, +1-208-939-4817, or Email Contact, all of STATS ChipPAC
Ltd.; or David Pasquale, Executive Vice President, of The Ruth Group,
+1-646-536 7006, or Email Contact, for STATS ChipPAC Ltd.

Web site:

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