Univers IDE supports Nios II Processor, delivering unparalleled debug capabilities
Fast RTL- and embedded software debugging with unique debug features
The heart of the Univers tools is a software IDE with unique debug capabilities setup to support multi-processor designs including its peripherals. The new Univers ISS (Instruction Set Simulator) model of the Nios II processor supports these debug features. Adveda's debugger gives the designer full visibility and full controllability of the internal nodes. Some unique debug features include:
-- Simultaneous simulation (and debugging) of more Nios processors (or other processors, eg an ARM7TDMI) in multi-processor applications including all hardware-peripherals in one unified simulation environment. -- If a location (register, memory cell or variable) with an unexpected value is found during debugging, Univers will identify the effected source code, leaving no room for speculation and saving very valuable time. -- Breakpoints and watchpoints can be set at any place in the source code, assembly code, registers or memory locations without affecting the simulation speed and will stop all processors at the same time. -- When a simulation has stopped (eg. By a breakpoint in an error routine), the user has the capability to simulate backwards through the source code, make a change and continue the simulation. Fast HW/SW Co-verification with 'accelerated RTL models'
Univers offers a unified verification solution, which enables simulation of embedded software in conjunction with hardware peripherals connected to the processors. You can use the RTL code of these hardware peripherals and the Univers RTL Modeler will automatically create a fast simulation model which will run typically 10 to 100 times faster than an RTL simulator. Moreover, these fast RTL models can be seamlessly attached to the Univers ISS models and allow to verify the embedded software in combination with the exact representation of the peripherals at a very high simulation speed. This will significantly improve the 'first-time-right' for such designs. An example of the speed of the RTL models, the VHDL code of the Nios II processor itself runs at 95K cycles/second.
"As FPGA designs are rapidly becoming as complex as ASIC designs, Adveda also decided to penetrate the FPGA market," said Cor Schepens, CEO of Adveda. "With the Nios II processor, Altera provides its customers with the option to quickly build very complex multi-processor embedded systems on an FPGA. Such systems require good simulation tools, as only debugging the embedded software in a prototype board is absolutely inadequate."
"The unique simulation and debug capabilities of Adveda's Univers toolset will allow our customers to dramatically improve the design time of the embedded software," said Chris Balough, director of software and Nios marketing at Altera. "Adveda's accelerated RTL models further provide our customers with the ability to debug with full visibility and full controllability their software by using their own set of hardware peripherals."
Pricing and Availability
Univers pricing starts at euro 1395 ($1825) and it contains a free ISS model of the Nios II/e processor, when bought before June 1, 2005. An evaluation copy of the Univers software can be downloaded from http://www.adveda.com/download/index.html.
The Nios II processor is available royalty-free from Altera as part of development kits featuring Cyclone, Stratix, and Stratix II FPGA's and upcoming Cyclone II development kits. A downloadable evaluation version is available from the Altera web site at: http://www.altera.com/niostestdrive.
Adveda enables both HW- and SW- developers to close the SOC verification gap by offering fast and fully integrated simulation and debugging tools. With these tools both the hardware and software of a System-On-Chip or complex FPGA can be verified within one environment. For more information visit http://www.adveda.com/.
CONTACT: Cor Schepens of Adveda, Phone: +31-40-2912385,
Cell: +31-6-43012712, Email Contact
Web site: http://www.adveda.com/