Zarlink Introduces World's Smallest Digital Timing Chip for SONET/SDH Line Cards

- DPLL (digital phase locked loop) provides best combination of features, jitter performance and small size for high-speed networks

OTTAWA, Nov. 30 /PRNewswire-FirstCall/ -- Zarlink Semiconductor (NYSE/TSX:ZL) today introduced the ZL(TM)30108, the world's smallest DPLL for optical line cards operating at rates up to OC-3/STM-1. The device delivers unparalleled features in a tiny footprint for the carrier-class transport of voice, data and multimedia traffic across high-speed networks.

Measuring just 5 mm (millimeters) x 5 mm, the ZL30108 DPLL addresses dense line card "real estate" constraints. The device may be used in combination with Zarlink's family of analog PLLs to provide an end-to-end timing and synchronization solution for higher-speed SONET/SDH networking equipment. For example, the ZL30108 DPLL and ZL30415 analog PLL provide an easy-to-implement, compact solution for OC-12/STM-4 line cards.

"The ZL30108 timing chip is the 'total package' in the industry's smallest footprint. It combines features such as jitter filtering and hitless reference switching and delivers optimized performance when used with a Zarlink analog PLL, together with jitter capabilities to meet OC-3/STM-1 requirements," said Darren Ladouceur, marketing manager, Timing and Synchronization, Zarlink Semiconductor. "Competing devices do not provide the same mix of performance and features, and none equal its extremely small size."

Major equipment manufacturers have already selected the ZL30108 DPLL for design into routers and multiservice access platforms.

Essential features for OC-3/STM-1 line cards

The ZL30108 DPLL provides high-performance line card synchronization that surpasses all OC-3/STM-1 specifications, with integrated features including reference monitoring, reference switching, automatic holdover, and jitter filtering and shaping.

The device accepts two input references, synchronizing to 8 kHz, 2 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz, or 19.44 MHz reference input frequencies. Each input is continuously monitored for frequency accuracy and pulse quality. The ZL30108 chip allows designers to monitor references using an inexpensive 20 ppm (parts per million) or 32 ppm crystal oscillator.

When a problem is detected in the reference clock, the device's reference switching capability enables systems to switch between timing references to avoid service interruption. If the network synchronization source is temporarily lost, the ZL30108 digital PLL switches automatically into holdover mode, and continues to generate output clocks based on data collected from past reference signals. The DPLL delivers exceptional holdover performance, with frequency accuracy of 0.01 ppm.

The ZL30108 chip provides a 19.44 MHz (SONET/SDH) clock output with jitter performance of better than 24 psRMS (picoseconds root mean square), delivering significant jitter margin versus OC-3/STM-1 specifications. The device also produces an 8 kHz framing pulse and 2 kHz multi-frame pulse with less than 0.5 nspp (nanoseconds peak-to-peak) intrinsic jitter.

Patented jitter shaping technique

With the rollout of increasingly complex network architectures and higher- speed transmission systems, designers must use combinations of digital and analog PLLs that work in tandem to deliver superior timing functionality and performance that meets the demands of carrier-grade equipment.

Typical DPLLs produce wideband phase noise across all frequencies, increasing the filtering demands on adjacent analog PLLs and degrading overall jitter performance. Zarlink's innovative jitter shaping technique effectively filters low-frequency phase noise, allowing designers to focus the analog PLL on its core attribute - eliminating high-frequency phase noise. Using this patented technique, jitter from the ZL30108 DPLL can be shaped so that it produces lower jitter, or is easily filtered by a Zarlink analog PLL for higher frequency applications.

Standards compliant

The ZL30108 DPLL generates low-jitter output clocks that meet Telcordia GR-253-CORE jitter specifications for OC-3 and comply with the ITU-T (International Telecommunication Union-Telecommunications) G.813 STM-1 specifications.

Pricing and availability

The ZL30108 chip is in volume production, and offered in a 5 mm x 5 mm, 32-pin QFN (Quad Flat No-Lead) package. In 1K quantities, the device is priced at US$12.50. For more information, please visit: http://products.zarlink.com/product_profiles/ZL30108 .

About Zarlink Semiconductor

For almost 30 years, Zarlink Semiconductor has delivered semiconductor solutions that drive the capabilities of voice, enterprise, broadband and wireless communications. The Company's success is built on its technology strengths, including voice and data networks, consumer and ultra low-power communications, and high-performance analog. For more information, visit http://www.zarlink.com/ .

  Certain statements in this press release constitute forward-looking
  statements within the meaning of the Private Securities Litigation Reform
  Act of 1995. Such forward-looking statements involve known and unknown
  risks, uncertainties, and other factors which may cause the actual
  results, performance or achievements of the Company to be materially
  different from any future results, performance, or achievements expressed
  or implied by such forward-looking statements. Such risks, uncertainties
  and assumptions include, among others, the risks discussed in documents
  filed by the Company with the Securities and Exchange Commission.
  Investors are encouraged to consider the risks detailed in those filings.

  Zarlink, ZL, and the Zarlink Semiconductor logo are trademarks of Zarlink
  Semiconductor Inc.

CONTACT: Zarlink: Ed Goffin, Media Relations,
(613) 270-7112, Email Contact; United States: Natalie Sauve,
High Road Communications, (613) 236-0909, Email Contact; Europe:
Simon Krelle, Pinnacle Marketing Communications, 44 1908 2355 22,
Email Contact




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