MILPITAS, CA--(Marketwired - June 06, 2016) - Open-Silicon, a system-optimized ASIC solution provider, today announced that it will present a technical paper and two posters, and demonstrate its breadth of ASIC solutions at the Design Automation Conference (DAC), June 6-8, 2016 in Austin, Texas.
- Breaking Through "The Memory Wall" -- HBM IP Subsystem
Tuesday June 7, 3:30pm - 5:00pm, Ballroom G (IP Track: Evolving IP Interconnects & Verification)
- Physical Planning of I/O Interface for 3D Stacking of Packaged Devices
Monday, June 6, 5:00pm - 6:00pm, Exhibit Floor (Design/IP Track Poster Session)
- Die Sizing Bound by Peripheral Bumps and IPs
Tuesday, June 7, 5:00pm - 6:00pm, Exhibit Floor (Design/IP Track Poster Session)
Booth Demonstrations: #2431, Exhibit Floor
- IoT ASIC Platform - Demonstrates end-to-end communication between sensor hubs and a cloud platform through a gateway device. Depending upon the type of radio technology, the sensor hubs can be used outdoors, on the factory floor or inside a room. This Industrial IoT system setup is part of Open-Silicon's Spec2Chip IoT Platform, which allows IoT ASIC designs to be evaluated at the system level.
- 28G SerDes Evaluation Platform - Enables the rapid deployment of chips and systems for high-bandwidth networks. The platform includes a full board with packaged 28nm test chip, software and characterization data. The chip integrates a 28Gbps SerDes quad macro, using physical layer (PHY) IP and meets the compliance needs of the CEI-28G-VSR, CEI-25-LR and CEI-28G-SR specifications.
- HMC 2.0 Memory Controller ASIC IP Platform - Allows quick evaluation of the HMC technology and performance testing of the HMC links. Based on the Xilinx Virtex-7 FPGA, this platform includes a fully validated design that integrates an HMC controller exerciser functions.
- 2.5D SoC Solution Platform - Demonstrates a functional system-on-chip (SoC) solution featuring two 28nm logic chips, with embedded two dual core 1GHz ARM Cortex™-A9 ARM processors, connected across a 2.5D silicon interposer.
- Comprehensive HBM Gen2 IP Sub-system Solution - This solution is now available for 2.5D ASIC design starts and also as licensable Intellectual Property (IP). Open-Silicon's IP fully complies with the HBM-Gen2 JEDEC® standard. The IP translates user requests into HBM command sequences (ACT, Pre-Charge) and handles memory refresh, bank/page management and power management on the interface. The IP includes the PHY and custom die-to-die I/O needed to drive the interface between the logic-die and the memory die-stack on the 2.5D silicon interposer.
Open-Silicon transforms idea into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers' products by innovating at every stage of design -- architecture, logic, physical, system, software, and IP -- and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing, and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed over 300 designs and shipped over 120 million ASICs to date. Privately-held, Open-Silicon employs over 250 people in Silicon Valley and around the world. www.open-silicon.com
Open-Silicon is a trademark and service mark of Open-Silicon, Inc. registered in the United States and other jurisdictions. All other trademarks are the property of their respective holders.
Contact Information: Purvi Shenoy Open-Silicon 408-240-5772 Email contact
Media Contact: Jennifer DeAnda 208-794-7113 Email contact