Low-Voltage Devices Among Seven New PECL Products Replacing Discontinued Agere Devices
The 3.3-V TB3R1 and TB3R2 quad differential PECL receivers offer a low- voltage migration path for designers who have previously used 5-V supply PECL devices. Five other devices -- the TB5D1M, TB5D2H, TB5R1, TB5R2 and TB5T1 -- have combined features to replace nine former Agere PECL devices. The devices match the original Agere pinouts, allowing for plug-in replacement. Each new device offers 3-kV HBM and 2-kV CDM electrostatic discharge (ESD) protection and an operating temperature range of -40 degrees C to 85 degrees C.
Key Features Quad Differential PECL Drivers (TB5D1M and TB5D2H) -- Translate PECL input levels to TTL output logic levels -- 5.0-V or 3.3-V supply operation -- (TB5D1M) Surge protection on differential outputs -- (TB5D2H) No line loading when Vcc = 0 -- Three-state output with a third-state level of less than 0.1 V -- Logic inputs include internal pull-up resistors of approximately 40 kOhm that are connected to Vcc to ensure a logical high level input if the inputs are open circuited. Quad Differential PECL Receivers (TB5R1, TB5R2, TB3R1, TB3R2) -- Translate PECL input levels to TTL output logic levels -- 5-V supply (TB5R1, TB5R2) -- 3.3-V supply (TB3R1, TB3R2) -- 50 mV hysterisis (TB5R1, TB3R1) -- Preferred state output (TB5R2, TB3R2) -- Power-down loading characteristics of the receiver input circuit are approximately 8 kOhm relative to the power supplies to prevent loading the transmission line when the device is powered down. -- Enable inputs include internal pull-up resistors of approximately 40 kOhm connected to Vcc to ensure a logical high level input if the inputs are open circuited. Dual Differential PECL Driver/Receiver (TB5T1) -- 5-V supply -- Translates TTL input levels to differential PECL output levels (driver) or converts PECL input levels to TTL output levels (receiver). -- Logic inputs include internal pull-up resistors of approximately 40 kOhm that are connected to VCC to ensure a logical high level input if the inputs are open circuited. -- Power-down loading characteristics of the receiver input circuit are approximately 8 kOhm relative to the power supplies to prevent loading the transmission line when the device is powered down. -- Each pair has its own common-mode enable control, allowing serial data and a control clock to be transmitted and received on a single circuit. -- In circuits with termination resistors, the line remains impedance- matched when the circuit is powered down. Available Today
The PECL translator devices are available now from TI and its authorized distributors. Packaging and suggested resale pricing listed below.
Part Number and Description Packages Price 1ku resale TB5D1M Quad driver with lightning SOIC, 7.20 protection (5V and 3.3V) Gull-wing TB5D2H Quad driver with no line SOIC, 7.20 loading with Vcc=0 Gull-wing (5V and 3.3V) TB5R1 Quad receiver with 50mV SOIC, 7.20 Hysteresis (5.5V) Gull-wing TB5R2 Quad receiver with preferred SOIC, 7.20 state output (5V) Gull-wing TB5T1 Dual differential SOIC, 7.20 transceiver (5V) Gull-wing TB3R1 Quad receiver with 50mV SOIC 8.65 Hysteresis (3.3V) TB3R2 Quad receiver with preferred SOIC 8.65 state output (3.3V)
The PECL translators join other TI interface and clocking products meeting designers' needs in PECL to TTL translation applications, such as the CDCM1804 and CDCM1802 clock buffers, each of which provides both a LVPECL output and a LVCMOS output.
For more information on finding the most appropriate bus interface solution for today's advanced system architectures, please refer to the "Comparing Bus Solutions" application report available at http://www.ti.com/sc04173b .
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