Altera Demonstrates Industry's First 32-Gbps Transceiver with Leading-Edge 20 nm Device

Demonstration Highlights Latest Success in Altera’s 20 nm FPGA Early Access Program

San Jose, Calif., April 8, 2013 -- Altera Corporation (NASDAQ: ALTR) today announced the company achieved another significant milestone in transceiver technology by demonstrating the industry’s first programmable device with 32-Gbps transceiver capabilities. The demonstration uses a 20 nm device based on TSMC’s 20SoC process technology. This achievement validates the performance capabilities of 20 nm silicon and is a positive indicator to the more than 500 customers in Altera’s early access program who are looking to use next-generation Altera devices in the development of performance demanding, bandwidth-centric applications. A  demonstration video showing the industry’s first operational 20 nm transceiver technology operating at 32 Gbps is available for viewing on Altera's website at  www.altera.com/32gbps-20nm.

Demonstrating 32-Gbps transceiver data rates provides Altera insight into how high-performance transceiver designs behave on TSMC's 20SoC process. The transceiver technology Altera is demonstrating today will be integrated into its 20 nm FPGA products, fabricated on TSMC’s 20SoC process. These devices enable customers to design next-generation serial links with the lowest power consumption, fastest timing closure and the highest quality signal integrity. Altera has a proven track record in integrating leading-edge transceiver technology into its devices. Altera is the only company today shipping production 28 nm FPGAs with monolithically integrated low-power transceivers operating at 28 Gbps. Being the first FPGA vendor to reach the 32-Gbps milestone in 20 nm silicon further extends Altera's leadership in transceiver technology.

The  demonstration video on Altera’s web site shows 20 nm transceivers operating at 32 Gbps with just over nine picoseconds of total jitter and extremely low random jitter of 240 femtoseconds. The results show good margin to key industry specifications requited for next-generation 100G systems.

“Today’s news represents a significant milestone for the industry and for the transceiver development team at Altera,” said Vince Hu, vice president of product and corporate marketing at Altera. “These 20 nm devices contain the key IP components that will be included in our next-generation FPGAs and validating them now provides us confidence we will deliver to the market 20 nm FPGAs on schedule.”

Altera’s next-generation transceiver innovations enable system developers to support the rapidly increasing amount of data that is being transmitted through the world’s networks. The transceivers in Altera’s next-generation devices will drive more bandwidth with lower power per channel versus the previous nodes and will support increasing port density by interfacing directly to 100G CPF2 optical modules. 

About Altera

Altera® programmable solutions enable system and semiconductor companies to rapidly and cost effectively innovate, differentiate and win in their markets. Find out more about Altera's  FPGAsSoCsCPLDs and  ASICs at  www.altera.com


Contact:

Steve Gabriel 
Altera Corporation 
Tel.: +408-544-6846 
Email Contact 




Review Article Be the first to review this article
Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Diversity: Really, who cares
More Editorial  
Jobs
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Methodology Automation Engineer for EDA Careers at San Jose, CA
DDR 3-4-5 Developer with VIP for EDA Careers at San Jose, CA
Proposal Support Coordinator for Keystone Aerial Surveys at Philadelphia, PA
Upcoming Events
11th International Conference on Verification and Evaluation of Computer and Communication Systems at 1455 DeMaisonneuve W. EV05.139 Montreal Quebec Canada - Aug 24 - 25, 2017
The Rise of Mechatronics at Dassault Systèmes San Diego 5005 Wateridge Vista Drive San Diego CA - Sep 12, 2017
The Rise of Mechatronics at Buca di Beppo - Pasadena 80 West Green Street Pasadena CA - Sep 13, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy