SpringSoft Technology Newsletter - March 2010
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SpringSoft Technology Newsletter - March 2010

Welcome to the SpringSoft Technology Newsletter. This is a monthly e-mail newsletter distributed to our customers, partners, and friends to provide information on our Novas Verification Enhancement and Laker Custom IC Design technologies. We hope the information in this newsletter will help you to use our products more effectively in your design and verification environments.

Please see the links at the end of this newsletter for subscription information or to provide feedback that will help us improve future editions.

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Verification Tips:


Integration with Verdi Speeds Certitude Setup and Eases Analysis and Debug 

The CertitudeTM Functional Qualification System identifies holes and weaknesses in the verification environment that can let RTL bugs slip through the process undetected.  With the release of version 2010.04 in April, VerdiTM users will be able to leverage their existing Verdi environment to minimize Certitude setup effort and analyze the results of functional qualification quickly and efficiently using Verdi's powerful debug features.

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New Essential Signal Analysis Result Format along with Enhanced Essential Signal Dumping Flow  

The Essential Signal analysis and dumping flow in the SilotiTM Visibility Automation System was refined in the Novas 2010.01 release. The purpose of the change is to make the usage smoother. It enables users to dump Essential Signal FSDB files in the full dump environment without having to touch and recompile the design. Also, the output of Essential Signal Analysis is changed from a text file to a binary database (ESDB).

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Reducing Memory Usage when Using Simulation Model in Behavior Analysis   

In the previous Behavior Analysis flow, the symbol library mode is recommended over the simulation model to get better performance and memory usage. This is because when the Behavior Analysis engine uses the simulation model, it will look into the library cell to get its equation which consumes a large amount of memory, especially in big gate-level designs.

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Custom IC Design Tips:


Interoperable PCell Standard 1.0 Released by IPL Alliance

By now, you may know that the IPL (Interoperable PDK Libraries) Alliance has released the first interoperable PCell standard. What you may not know is that SpringSoft is a founding member of the IPL. The release of the Standard is the culmination of more than two years of effort by the founders and members of the IPL. You can see and download this new Standard on the IPL web site at www.iplnow.com. The download includes a generic 90nm interoperable process design kit (iPDK), reference design, sample PyCellTM library (including PyCell source code), User's Guide, and a Developer's Guide that includes information about how to create PCells that are interoperable with most major EDA tools running on OpenAccess.

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Technical Articles:


A Silicon-proven Interoperable PDK - EDADesignline.com; March 5, 2010

On July 21, 2009, TSMC announced the availability of the industry's first interoperable process design kit (iPDK). The kit was fully validated on TSMC's 65 nanometer (nm) MS/RF process and all major EDA vendors announced their support, including Cadence, Ciranova, Magma, Mentor, SpringSoft, Synopsys, and others. On March 24, 2010, the Interoperable PDK Libraries (IPL) Alliance of which TSMC is a member, released the IPL 1.0 standard, and made the underlying technology for the TSMC iPDK available to the entire industry.

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Help! - All of My Simulations are Passing! - EDADesignline.com; February 18, 2010

This statement of anguish - rarely uttered in the annals of functional verification history - is certainly absurd on its face. After all, verification engineers continually strive for the holy grail of clean regressions, toiling day-after-day to cleanse the system of failing tests on their way to tape-out nirvana. But pause and consider for a moment a world in which passing tests are not an indicator that all is well, but rather a warning flag that not enough functionality is being tested, vital checks that confirm proper operation of the design are missing, or - worse yet - problems in the verification infrastructure are masking test failures and hiding RTL bugs merrily making their way to fabrication. Such musings might lead one to ask, who's verifying the verification environment?

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All Worldwide Support Consolidated To One Site

No matter where you are worldwide, you can now find SpringSoft's top rated support in one place. Just go to http://www.springsoft.com/support

The most recent product releases are:


  • Novas Verdi - 2010.01
  • Novas Siloti - 2010.01
  • Certitude - 2010.01

IC Design & Layout:

  • Laker db - 2009.12
  • ADP db - 2009.12
  • Laker OA - 2010.02
  • T1 - 3.2T1v5

Look for the upcoming versions:


  • Novas Verdi - 2010.04
  • Novas Siloti - 2010.04
  • Certitude - 2010.04

IC Design & Layout:

  • Laker db - 2010.03
  • ADP db - 2010.03
  • Laker OA - 2010.05

Go to www.springsoft.com/support to update your versions.



SpringSoft Integrates New Automation Technologies into Certitude Functional Qualification System - March 1. 2010

HSINCHU, Taiwan, March 1, 2010 - SpringSoft, Inc. (TAIEX: 2473), a global supplier of specialized IC design software, today introduced powerful methodology and ease-of-use advancements with the latest release of its CertitudeTM Functional Qualification System. The Certitude system removes verification uncertainty and accelerates functional closure for complex intellectual property (IP) and system-on-chip (SoC) designs with unique automation technologies that qualify the thoroughness of verification environments and identify weaknesses that could allow bugs to go undetected.

<Read more>

SpringSoft Unveils Unique Automated Custom Digital IC Place and Route Tools - March 15, 2010

HSINCHU, Taiwan, March 15, 2010 - SpringSoft, Inc. (TAIEX: 2473), a global supplier of specialized IC design software, today introduced two new products aimed at addressing the increasing challenge of designing custom chips that contain both analog and digital circuitry. Building on its expertise in automated custom design with its LakerTM suite of custom IC design solutions, the company unveiled its Laker Custom Row Placer and Laker Custom Digital Router. The tools are fully compatible with the Laker Custom Layout Automation System, allowing designers to work within a single custom IC layout environment to efficiently place-and-route both digital custom cells and standard cells for either mixed-signal or custom digital designs.

<Read more>

Upcoming Events:


Joint webinar with ClioSoft

Effective Data Management for AMS Design Teams

March 30, 2010 @ 11AM PDT

Register Here!


  • Duncan McDonald, Product Marketing for Custom IC Design Solutions, Springsoft Inc.
  • Karim Khalfan, Technical Marketing Engineer, ClioSoft, Inc.


Large and geographically dispersed AMS design teams face the challenges of collaborative design. Tools and techniques must be adopted to effectively share the large volume of frequently changing design data between the team members. A Hardware Configuration Management (HCM) system integrated seamlessly into the design flow is key to avoiding errors, delays and re-spins. This seminar explores the pitfalls of using ad-hoc methods for sharing data and how an HCM system can streamline the design flow and improve team productivity. The principles are illustrated using ClioSoft's SOS HCM system seamlessly integrated into SpringSoft's Laker Custom IC Design flow.


  • Challenges of managing design projects
  • Traditional techniques of sharing design data
  • Streamlining design flow & collaboration with HCM
  • Integrated ClioSoft HCM for Laker Flow
  • Product Demonstration
  • Q & A

2010 SNUG San Jose Design Community Expo

March 29-31, 2010
Santa Clara Convention Center
Find us at Booth #23

TSMC Technology Symposium

April 13, 2010
San Jose, CA

SpringSoft Community News!

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