October 2009

Welcome to the October issue of IP Times – your source for semiconductor Intellectual Property (IP) news, trends, and developments – from the industry’s trusted IP partner. Learn about the latest news from Virage Logic!

Resource Center

Upcoming STAR™ Memory System Class – November 10-11, 2009
Sign up today for this extensive two-day course featuring lectures, hands-on tutorials, and labs that instruct you on how to integrate the STAR Memory System into your System-on-Chip (SoC) designs and accelerate your silicon success. STAR Memory System customers have improved yields by up to 250%, so don’t miss this opportunity to learn how you can effectively implement this solution to help increase yields. There is still time to register!

SiPro™ Advanced Interface IP Solutions – Video Demo
Learn more about Virage Logic's SiPro – a complete production-proven PCI Express Gen1 / Gen2 solution at the most advanced process nodes to help minimize risk, improve time-to-market, reduce die size and reduce power. Watch the video!

New! Virage Logic Power Forward Initiative Low-Power Summit Presentations
Virage Logic recently delivered two informative presentations at the Low-Power Summit. Download a copy of " Power Optimization with Standard Cell Logic Blocks," or " Implementation of Advanced Power-Aware Memory Compilers."

Virage Logic in the News

Virage Absorbs a Key Piece of NXP: Signs for the Future of IP? – Ron Wilson, EDN
In a startling move announced this morning, growing semiconductor intellectual property vendoe announced that, through an unusual and complex agreement, it has in effect acquired much of the technological heart of NXP Semiconductors. The agreement, billed by the two companies as a strategic alliance, cannot but bring profound change to both organizations. Read the article.

Implementing an All-Digital PHY and Delay-Locked Loop for High-Speed for DDR2/3 Memory Interfaces – EDN
Area, power, performance, and time to market are all critical design concerns in a competitive marketplace. A new, all-digital approach to implementing high-speed PHY logic and a DLL offers a path to addressing increasingly stringent market requirements. This article will outline the methodology behind an all-digital PHY+DLL and describe several key implementation techniques used when transitioning to a new standard cell library. Read the article.

How to Reduce Memory Power in SoC Designs – Embedded.com
Unlike regular design registers that only dissipate dynamic power when they are written, memories dissipate dynamic power when they are either read or written. As such, removing redundant reads or writes can result in significant dynamic power reduction. We discuss sequential analysis techniques used to accomplish this. Read the article.

Upcoming Industry Events

As the industry’s trusted semiconductor IP partner, Virage Logic participates in a variety of global industry events to help educate the SoC design community on the latest advanced IP technology. See below for a list of upcoming events where you can hear Virage Logic’s IP experts address the complex issues facing the industry today.

International Test Conference (ITC)
November 1-6, 2009 – Booth #417
Austin Convention Center, Austin, Texas
Increase your chip bring-up efficiency with Virage Logic at ITC! This is your opportunity to learn more about Virage Logic's powerful new solution to help increase chip bring-up efficiency. Virage Logic will showcase a live demonstration of this new option to its industry standard STARTM Memory System for post silicon bring-up and system debug. Virage Logic’s Dr. Yervant Zorian, Vice President and Chief Scientist, will be a featured speaker, panelist and moderator at these informative ITC events.

Sunday, November 1st   
Tutorial 4: System-in-Package Test Strategies
8:30am - 4:30pm

Tuesday, November 3rd
Panel 3: Testing of 3-D Chips: Is There Anything New Under the Sun?
4:00pm - 5:30pm

Wednesday, November 4th
Embedded Tutorial 1: Testing 3-D Chips Containing Through-Silicon Vias
8:30am - 10:00am

Session 7: Embedded Memory Test & Repair
8:30am - 10:00am

Virage Logic Exhibitor Presentation: An End-to-End Solution for Yield Optimization
10:00am - 10:30am

Management Session: Decision Making Trade-Offs and Choices for Testing Today's Most Complex Chips
4:00pm - 6:00pm

Thursday & Friday, November 5th & 6th
DRV: 2nd IEEE International Workshop on Design for Reliability and Variability
2:00pm - 9:00pm

TVHSAC: IEEE International Workshop on Test and Validation of High-Speed Analog Circuits
2:00pm - 9:00pm

Be sure to visit the Virage Logic advanced semiconductor IP experts in booth #417 and register for a chance to win a Radeon HD 4477 Graphics Card.   Register.

International System-on-Chip Conference (SoC)
November 4-5, 2009
Radisson Hotel, Newport Beach, California
Virage Logic will be participating with a featured panelist at the upcoming SoC Conference. Come and hear our Virage Logic IP expert address the topic: "Improving Design Productivity and IP Quality Through the Effective Use of Standards for Complex Multicore SoCs."   Register.

Upcoming VIP Partner Events

Virage Logic’s VIP Partner Program brings together technology and business alliances with our industry partners for the benefit of our mutual customers. As part of the VIP Partner Program, Virage Logic supports our partners’ global events, such as the ones listed below.

MIPS Ecosystem Expo – MIPS Technical Seminar
November 3, 2009
Avenue Conference Center, Airport City, Israel
Virage Logic will be participating at the upcoming MIPS Ecosystem Expo. This important event features partners, such as Virage Logic, sharing how they collaborate with MIPS Technologies. Don’t miss Virage Logic’s IP experts who will be on hand to discuss the company’s broad portfolio of advanced semiconductor IP with you. Register.

Virage Logic Membership Has its Access Privileges

Become a Virage Logic Member for exclusive access to Foundry-Sponsored IP, technical documentation, and much more! It only takes a few minutes to become a Virage Logic Member. Sign up today and begin enjoying the benefits of Virage Logic Membership.

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