The Economies of Outsourcing

Verific


The economies of outsourcing

Why you should not develop and maintain your own (System)Verilog and VHDL front-ends

In his 2000 book 'Living on the Fault Line', high-tech guru Geoffrey Moore (of 'Crossing the Chasm' fame) makes an eloquent case for corporations to focus on Core and outsource Context. In Moore's view, Core are the activities that directly affects the competitive advantage of an organization, in other words differentiate it from the competition. All other activities, and those are often the bulk of an organization, are Context. The important message, of course, is that one should outsource its Context and focus its best and brightest on its Core. The good news is that one company's Context is another company's Core. An example is the paper multiplication industry. Having a photocopy machine at work is handy, but once a manual needs to be reproduced for customer ship wouldn't you rather go to Kinko's. They pick up and deliver your materials, keep their machines humming 24 hrs a day, and are a lot cheaper than you burning the midnight oil changing your office copier's toner. The time saved should be used on planning your next product.

The Core versus Context discussion is often related to the Buy versus Make question. If a good solution is available for a well-defined problem, why bother re-inventing the wheel and providing a home-grown solution ? Chances are that the task at hand is Context to your application anyhow. And, through purchase, you may very well accelerate introduction of your Core product by many months.

This concept of Core versus Context is applicable to many industries, including Electronic Design Automation (EDA). Most EDA companies have already outsourced some Context activities in their EDA tools, such as License Managers. Why would anyone bother writing their own software for licensing management if the same can be achieved with production proven software from Acresso, a third party software company selling FlexLM, or Reprise who has a competing offering. It will never make a difference during the evaluation and purchase decision of the EDA tool, the company's Core offering. (The argument can even be taken a step further. Not using the industry standard Licensing Manager may be considered a negative by the customer. After all, now the customer has to learn and manage a new licensing mechanism.)

Verilog and VHDL front-ends, for long the Core of companies such as Synopsys (HDL Compiler) and Cadence (Verilog-XL), have entered the ranks of Context . Nowadays, EDA products in such diverse fields as design for test, formal verification, synthesis, simulation, and emulation all require (System)Verilog and VHDL parsers / elaborators, supporting identical, non-discriminating IEEE standards.

As many have found out, building HDL parsers and elaborators is not an altogether easy task. Several man years, not counting future debug activity, typically are required to put a reliable system together. And at the end, it will not differentiate the product from the competition because they all support the same IEEE standards. In Moore's view, a much preferred solution would be to acquire a production proven, fully debugged HDL front-end and focus your engineering team on your Core Competency, whether that is in simulation, formal verification, emulation, hardware acceleration, or design for test.

To find out if your HDL front-end is Core or Context and whether outsourcing it may be for you, you can ask yourself the following questions:

  • Can you distinguish your company from the competition with your HDL frontend ?
  • Does it make your company more competitive ?
  • Do you have the expertise in house to build and support it ?
  • Are you prepared to support future language extensions ? Are you ready for SystemVerilog ?
  • Do you want to get your product out to market earlier ?
Chances are you find your Verilog and VHDL support are merely Context to your application, necessary but non-discriminating. And that may be the time to start looking for a solution from a company that makes HDL front-ends its Core and has the customer base to prove it.

About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, is a leading provider of SystemVerilog, Verilog and VHDL front-end software founded in 1999 by EDA industry veteran Rob Dekker. Verific's software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: www.verific.com.

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.


Verific

Reviews:
Review Article
  • The Economies of Outsourcing October 27, 2009
    Reviewed by 'J Pan'
    The article provides a thought over focusing on your core competence. I agree with the author's point. However, selling a complete product to the market place, you have to ensure the continuity of the availability of the Context - what if the vendor decides to exit, what if you need a quick fix or enhancement, etc. Will your product be jeopadized then?

      One person found this review helpful.

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