Apache Design Newsletter - Oct. 2011
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Apache Design Newsletter - Oct. 2011



Apache Technology Forum

Power and Reliability for 28nm IC Designs

The Apache Technology Forum is a comprehensive one-day technical seminar for chip, package and system designers to learn how Apache’s innovative power analysis and optimized solutions enable power-efficient, high-performance, noise-immune ICs and electronic systems. This interactive forum features industry leaders sharing best practices and real design examples of proven methodologies that address critical power and reliability challenges in advanced node designs. Deep technology tracks will focus on practical solutions to meet the power budgeting, power integrity and power induced noise reliability needs of 28nm and 3D-IC designs. For those unfamiliar with Apache, this is a chance to learn what we have to offer. For designers who know Apache, this is an opportunity to stay up to date with our award-winning low-power technology.

Topics Covered

  • Apache technology vision and roadmap
  • Introducing ANSYS
  • User experience: Low power design applications
  • User experience: Chip-Package-System co-design and co-analysis
  • User experience: Power and reliability for IP-based designs
  • Power and reliability challenges and solutions for 28nm and 3D-IC designs

Locations and Dates

  • Taiwan: November 30
  • Japan: December 2
  • Korea: December 6
  • China: December 8

Check our website for more information.

Ultra Low Power (Video)

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Upcoming Events

TSMC Open Innovation Platform
San Jose, CA
October 18, 2011

EPEPS 2011
San Jose, CA
October 23 - 26, 2011

ARM Technology Conference
Santa Clara, CA
October 25, 2011

MEPTEC 2.5D, 3D & Beyond
San Jose, CA
November 9, 2011

ARM Technology Conference
Hsinchu, Taiwan
November , 2011

Articles and Blogs

Popular Whitepapers

  • Advanced Modeling for Chip, Package, System Co-analysis/Co-optimization
  • Analysis of Low-Power Designs with Power Gate (MTCMOS) Circuits Using RedHawk™
  • Power and Signal Line EM Design and Reliability Validation Challenges
  • PathFinder™: Solution for Full-chip IC ESD Integrity
  • RTL Design-for-Power (DFP) Methodology
  • Technologies for Power, Signal, Thermal, and EMI Sign-off for Chip-Package-PCB Designs

To download Whitepapers from our website, click here. Valid account required.

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