"Cadence has been a pioneer in pattern-matching technology, and our long-time development partner for the GLOBALFOUNDRIES DRC+ flow," said Luigi Capodieci, fellow and director of DFM at GLOBALFOUNDRIES. "GLOBALFOUNDRIES offers the industry's first silicon-validated libraries of yield-critical patterns -- layout patterns that are known to fail on silicon -- for technologies at 32 nanometers, 28 nanometers and below. We rely on Cadence pattern classification technology to classify yield detractors into pattern families based on pattern similarity, including inexact patterns, to maximize the efficiency of DRC+. The innovative DRC+ verification flow, with the full-power of the industry leading Cadence Pattern Search and Matching Analysis, has been successfully used on several 32- and 28-nanometer production IC designs."
Many of the world's leading technology companies, including Rambus, have successfully applied the in-design DRC+ flow using the silicon-validated 28-nanometer pattern library from GLOBALFOUNDRIES. The core of the DRC+ flow is the two-dimensional shape-based pattern matching, which offers significant speed improvements in error detection and fixing.
The Cadence Pattern Search and Matching Analysis are embedded in Cadence Litho Physical Analyzer, Cadence Physical Verification System and the unified Cadence Virtuoso® custom/analog and Encounter® Digital Implementation System solutions. This offers designers the flexibility to leverage the in-design pattern matching and automatic fixing available in Encounter and Virtuoso, which correlates 100 percent with the signoff flow and has successfully been used on advanced node production chips.
"This was the first time we used the in-design approach to DFM, and the results were impressive," said Keith Windmiller, senior director of Design Technology at Rambus. "Our IP is at the forefront of advanced node design, so we enthusiastically embrace technology that reduces risk, reduces time-to-tapeout, and promotes silicon yield and predictability. Deployed with the GLOBALFOUNDRIES 28-nanometer DFM process, the Cadence in-design DRC+ solutions delivered up to 60 times faster DFM signoff than traditional methods, and essentially eliminated any significant issues at signoff. Based on those results, this is an approach we will continue to use in our advanced node designs."
"The Cadence in-design technology reflects our approach to Silicon Realization by moving traditional DFM steps into digital and custom implementation," said Wilbur Luo, group director, product marketing, Silicon Realization Group at Cadence. "This enables engineers to tackle potential manufacturing issues earlier in the chip development process -- before these issues become serious, costly problems at the manufacturing stage."
Cadence will be speaking about its unified Encounter digital flow, its unified Virtuoso AMS/custom flow, and DFM collaboration at 4:30 p.m. Aug. 30 at the Global Technology Conference in the Santa Clara Convention Center.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Cadence, Encounter, Virtuoso and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact: Dean Solov Cadence Design Systems, Inc. 408-944-7226 Email Contact