Averant Adds RTL and Gate Level Combinational Equivalency Checker

HAYWARD, Calif. — (BUSINESS WIRE) — August 1, 2011 — Averant Inc., the First In Formal™ leader in property verification of RTL designs for digital circuits, today announces the release of Solidify 5.4. Some of the highlights of this release are listed below.

  • Combinational Equivalency Checker. When proving two designs are equivalent, a significant portion of the two designs are combinationally equivalent. A fast combinational equivalency checker (CEC) is added to Solidify to catch such cases.
  • Improved Sequential Equivalency Checking (SEC). The SEC engines have been enhanced to provide speed-ups of several orders of magnitude in some cases, in addition to improved proving powers.

Release 5.4 also provides better System Verilog Design support, speed-ups in formal engines, improved reset sequence guessing, improved SEC debugging, improved protocol checking including ARM AMBA protocols, and bug fixes.

“Our Japanese customers have always been enthusiastic about Averant’s innovations in formal technologies,” commented Seiichi Nishio, COO of GAIA System Solutions Inc. “I am confident Averant’s leadership in being the first company to combine important and correlated formal technologies in one product will be well-received by our customers.”


Release 5.4 is available immediately.

About Averant

Averant Inc. is a privately held EDA firm specializing in formal verification of digital designs. Averant’s flagship product is Solidify, a robust platform for property, protocol, and automatic design checks – all without the need for simulators or test vectors. Averant’s tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, visit http://www.averant.com.


Averant, Inc.
Ramin Hojati, 510-205-9815
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