Docea Enhances What-if Power Analysis and Optimization for Architectures, Use Cases

  • Aceplorer Improves System-Level Performance and Power Trade Off Analysis Using Interoperability with Virtual Platforms 
  • New Demo Showcases Automatic Scanning of Power Reduction Techniques Efficiencies and Architecture Exploration

San Diego, CA, June 2, 2011 - At the 48th Design Automation Conference ( DAC), Docea Power, the design-for-low-power company that delivers software for power consumption and thermal analysis at the architectural level, will show and introduce an enhanced version of its flagship software product, Aceplorer 2.3, with a synthetic view for capturing the power architecture of complex designs. This enables what-if analysis and optimization for hardware architecture and the target applications’ use cases. Aceplorer models and optimizes electronic design power consumption, early in the design cycle, at the architectural level.

Aceplorer 2.3’s new features are built on top of a parameterized power models library. They allow users to set up a complex system design with any number of Intellectual Property (IP) cores and blocks, voltage clusters or clock domain distributions at a fraction of the time needed with any other methodology. The benefit is making more time available for in-depth exploration of the design space.

DAC Demonstrations

At DAC, Docea is demonstrating automatic scanning of power reduction techniques efficiencies on a design (dynamic voltage and frequency scaling (DVFS), clock gating, power gating and any combination thereof) and enabling architects to make better quality design decisions early in the process.

Docea Power’s Aceplorer interoperability with Synopsys Electronic System Level (ESL) products is being demonstrated at Synopsys’ Standards Booth. This interoperability facilitates the import of power-related information for building complex and accurate dynamic scenarios, using performance analysis conducted on virtual platforms.

When/Where

Product Demonstrations:

Monday-Wednesday, June 6-8, 2011, 9 am to 6 pm

Docea Booth #1912

Interoperability with Synopsys ESL products

Tuesday, June 7, 2011, 9 am to 12 pm,

Synopsys Standards Booth #3328

San Diego Convention Center, San Diego, CA


Information and Registration

To request a private demo, please register here.

To schedule a meeting with Docea Power, please email Ridha.hamza (a)doceapower.com or call +33 (0)4 27 85 82 97

For more information about Docea, please visit www.doceapower.com.

To register for DAC, please visit www.dac.com.

About Docea Power

Docea Power develops and commercializes a new generation of methodology and tools for enabling faster and more reliable power and thermal modelling at the electronic systems level. Its Aceplorer offers a consistent approach for executing architectural exploration and optimizing power and thermal behaviour of electronic systems at an early stage of a project. Docea’s customers include manufacturers of electronic systems, chips and boards targeting wireless, multimedia, consumer, networking and automotive applications. For more information: www.doceapower.com.

-end-

Press contacts

Europe: Chantal Cochini, l’Ops PR, +33(0)1 42 71 30 93, Email Contact

US: Georgia Marszalek, ValleyPR LLC, +1 (650) 345-7477, Email Contact

 




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