Real Intent Highlights Latest Technology for Advanced Sign-Off Verification at DAC 2011
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Real Intent Highlights Latest Technology for Advanced Sign-Off Verification at DAC 2011

SAN DIEGO, CA -- (MARKET WIRE) -- May 19, 2011 -- Real Intent Inc., the leading provider of software products that accelerate Advanced Sign-Off Verification of electronic designs, today announced it will highlight its latest technology and proven solutions at this year's 48th Design Automation Conference ( DAC) in San Diego, California, June 6-8, 2011. Real Intent will feature its Ascent™ XV solution, the industry's first and only solution for comprehensive X-verification and sign-off. Ascent XV isolates and eliminates functional bugs that are masked by X (or unknown value) propagation in Register Transfer Level (RTL) simulation and reduces gate-level simulation debugging due to mismatches between RTL and gate-level simulation results. Featured are the latest advances in Meridian™ CDC, the industry's flagship Clock Domain Crossing sign-off verification solution, and new capabilities within Ascent Lint, the industry's fastest and most accurate lint solution with links to automatic formal checks in Ascent IIV (Implied Intent Verification). Real Intent will also show Meridian DFT, its Design for Test verification solution, and PureTime™, its constraints management solution with glitch-aware exception verification.

See Demonstrations of Real Intent's Advanced Sign-Off Verification Products at DAC booth #2131

Demonstrations of Ascent Family, Meridian Family and PureTime solutions are available during exhibit hours, Monday through Wednesday, 9:00 AM to 6:00 PM, at Real Intent's DAC booth #2131, San Diego Convention Center.

Requests for private appointments in Real Intent's demo suites may be booked in advance of the show by sending email to Email Contact.

Panel: The Billion Dollar Question: How to Verify Billion-Gate Designs

Real Intent's CEO, Prakash Narain, will be participating in a DAC conference panel titled The Billion Dollar Question: How to Verify Billion-Gate Designs, which will be held on Wednesday, June 8, from 4:00 to 6:00 PM in Room 33ABC. This panel will discuss what solutions are crucial for verifying designs susceptible to complex failures arising from corner-case confluences of timing and functionality. The panel will debate the merits of emerging solutions for such self-contained verification problems that threaten to subvert the nominal "simulation plus STA" verification flow. Other speakers on the panel include: Dammy Olopade - Intel Corp.; Kathryn Kranen - Jasper Design Automation, Inc.; Dan Smith - NVIDIA Corp.; Rowland Reed - Qualcomm, Inc.; and Y.C. Wong - Broadcom Corp. The Chair of this session is Sandip Kundu - Univ. of Massachusetts, and the Organizer is Himanshu Bhatnagar - Mindspeed Technologies, Inc.

Information and Registration
For more information and to register for DAC, please visit www.dac.com.
To schedule a meeting or demonstration, please email Email Contact.
For more information about Real Intent and its products, please visit www.realintent.com.

About Real Intent
Real Intent is the leading provider of software products that accelerate Advanced Sign-Off Verification of electronic designs. The company provides comprehensive solutions for ensuring synchronization of communications between on-chip intellectual property (IP) cores, as well as detecting and eliminating potential complex failure modes of today's highly integrated Systems-on-Chips (SoCs). Real Intent's products lead the market in high performance, capacity, report accuracy and comprehensiveness, enabling fast and complete sign-off verification. For more information, please visit www.realintent.com.

Notes to editors:
Ascent, Meridian and PureTime are trademarks of Real Intent, Inc.
All other trademarks and trade names are the property of their respective owners.

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Georgia Marszalek
ValleyPR LLC for Real Intent
+1-650-345-7477

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