PathFinder Selected Winner of EDA Tools and ASIC Technologies Category
SAN JOSE, CALIF. – May 5, 2011 – Apache Design Solutions, a leading provider of innovative power analysis and optimization solutions that enable the design of power-efficient, high-performance, noise-immune ICs and electronic systems, today announced that PathFinder™ was selected as the winner of EDN Magazine’s Innovation of the Year Award in the EDA Tools and ASIC Technologies category. PathFinder is the industry’s first comprehensive electro-static discharge (ESD) physical integrity solution targeted at addressing the increasing reliability challenges faced by nanometer designs. The award winners were selected by a combination of EDN’s worldwide audience of electronics engineers and EDN’s editorial staff.
“Apache is pleased to win this award for PathFinder’s innovative technology solution that provides both layout-based ESD sign-off at the full-chip level and Spice accurate transistor-level dynamic simulation for circuit level macros,” said Dr. Andrew Yang, chief executive officer of Apache Design Solutions. “Over the past eight years, five of our products have been selected as finalists, and three of them have taken top honors, including RedHawk for full-chip dynamic power integrity, CPM for chip-package convergence, and now PathFinder.”
PathFinder’s full-chip capacity and layout-based GUI environment enables designers to perform early prototyping, circuit optimization, and ESD sign-off for Human Body Model (HBM) and Machine Model (MM) events. Based on integrated modeling, extraction, and simulation capabilities, PathFinder addresses the limitations of manual design validation processes and methodologies by automating the process and enabling exhaustive testing of every device and wire that can potentially fail from an ESD event. PathFinder helps designers identify the most vulnerable area of the design to meet their ESD guidelines and improve product yield
For circuit analysis of I/O, analog, and mixed-signal design, PathFinder also offers the industry’s only transistor-level dynamic ESD solution for validation of Charged Device Model (CDM) events. It efficiently simulates large-scale macros, including the impact of clamp’s snap-back characteristics, power/ground and substrate networks, and package parasitic with convergence property.
To learn more about Apache’s EDN Innovation Award winners, PathFinder, RedHawk™ and CPM™, and the rest of Apache’s portfolio of products that help advance low-power innovation,
visit us in booth #2448 at the upcoming Design Automation Conference (DAC), June 5-10, 2011, at the San Diego Convention Center in San Diego, California. Meet with our Power Team Experts to learn how Apache’s
IP Integration, and
Chip-Package-System (CPS) solutions can help meet your low-power requirements and reduce costs.
Apache Design Solutions, Inc. is a leading provider of innovative power analysis and optimization solutions that enable the design of power-efficient, high-performance, noise-immune ICs and electronic systems. Apache’s comprehensive suite of integrated products and methodologies advances low-power innovation and provides a competitive advantage for the world’s top semiconductor companies. The company’s differentiated software solutions help lower power consumption, increase operating performance, reduce system cost, mitigate design risks, and shorten time-to-market for a broad range of end-markets and applications. Headquartered in San Jose, California, Apache serves its customers with sales, support, and R&D offices worldwide. Visit Apache Design Solutions at www.apache-da.com.
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Apache Design Solutions
Yukari Ohno, (408) 457-2000, Email Contact
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