Real Intent Inc., the leader in automating the intelligence of formal techniques for design verification sign-off and a member of Synopsys VMM Catalyst Program, will demonstrate its electronic design automation (EDA) software at the Synopsys Users Group (SNUG®) Designer Community Expo (DCE). The SNUG DCE is an invitation-only networking event featuring Synopsys and its ecosystem partners from across the electronics industry.
Real Intent products are used to sign-off designs and constraints at key hand-off points throughout integrated circuit (IC) design and implementation. At SNUG DCE, Real Intent will demonstrate:
- Meridian CDC -- sign-off quality Clock Domain Crossing (CDC) verification;
- Ascent Lint -- high performance, low noise design linting;
- Ascent IIV (Implied Intent Verification) -- early functional verification for implied design intent;
- Ascent XV (X Verification) -- analysis and verification for X-related design bugs;
- PureTime -- constraints management with glitch-aware exception verification.
Real Intent will also showcase how its solutions work with Synopsys VCS simulator to enable Advanced Verification Sign-off for functional integrity and CDC integrity of large SoC designs.
Why See Real Intent's Demos:
Meridian CDC is the fastest, highest capacity and most precise solution for verification sign-off.
Ascent Lint is over 10 times faster than competing solutions while offering the highest accuracy.
Ascent XV is the only commercial solution for X verification.
Monday, March 28, 2011, 4:30-7:30pm
Hall B, Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, CA 95054
SNUG and DCE are by-invitation events for Synopsys customers only. Information about the Designer Community Expo is available on the SNUG Designer Community Expo (DCE) site.
To schedule a meeting or demonstration, please email Email Contact.
For more information about Real Intent and its verification products, please visit www.realintent.com.
About Real Intent
Real Intent is the innovator in automating the intelligence of formal techniques for electronic design verification sign-off. Its software dramatically improves functional verification efficiency and design quality for ASICs and FPGAs devices and is used by design and verification teams worldwide. www.realintent.com. Follow @RealIntent on Twitter.
Notes to editors:
Ascent, Meridian and PureTime are trademarks of Real Intent, Inc.
Synopsys, SNUG, and VCS are registered trademarks of Synopsys, Inc.
All other trademarks and trade names are the property of their respective owners.
Press Contact Georgia Marszalek ValleyPR LLC for Real Intent +1-650-345-7477 Email Contact