IEEE-ISTO Announces Forum to Evolve Interconnect Modeling Standard

PISCATAWAY, NJ -- (MARKET WIRE) -- Jun 07, 2010 -- IEEE Industry Standards and Technology Organization (IEEE-ISTO), the premier trusted partner of the global technology community for the development, adoption, and certification of industry standards, has entered into a partnership with Synopsys to form a technical advisory board to facilitate the evolution of Synopsys' Interconnect Technology Format (ITF) into an industry standard format for interconnect parasitic modeling.

The founding members of the Interconnect Modeling TAB (IMTAB) are representatives from industry-leading semiconductor companies, EDA companies and silicon foundries including Altera Corporation, AMD, Apache Design Solutions, GLOBALFOUNDRIES, LSI, Magma Design Automation, NVIDIA, Qualcomm, STMicroelectronics and Synopsys.

IMTAB will join IEEE-ISTO's expanding federation of member programs. IMTAB will leverage ITF as the basis of interconnect modeling standard and drive its development to address future industry demands. ITF will be available industry-wide through an open source license agreement with Synopsys. IEEE-ISTO will manage the operations of IMTAB.

"IEEE-ISTO has a proven track record launching and promoting new initiatives that foster market acceptance of standards, such as ITF," said Rich Goldman, vice president of corporate marketing and strategic alliances at Synopsys. "IEEE-ISTO's guidance and support will enable IMTAB to successfully meet its goals during formation and beyond."

IMTAB marks the second Technical Advisory Board collaboration between IEEE-ISTO and Synopsys. The Liberty Technical Advisory Board was formed in 2008 and maintains the Liberty library modeling format -- the semiconductor industry's most widely accepted library standard.

"Open collaboration is a critical component to the successful market adoption of industry standards," said Peter Lefkin, marketing and business development executive, IEEE-ISTO. "IEEE-ISTO looks forward to facilitating the evolution of ITF."

About ITF
Synopsys' Interconnect Technology Format (ITF) provides detailed modeling of interconnect parasitic effects, enabling designers to perform accurate parasitic extraction for timing, signal integrity, power and reliability signoff analysis. ITF offers a flexible and innovative format to accurately model the effects of increased process variation at advanced process technologies. ITF has been evolving for more than 10 years and is the semiconductor industry's most widely used interconnect modeling format. It is supported by leading semiconductor foundries and integrated device manufacturers, and is proven on thousands of production designs.

The latest specifications for the open source licensed ITF can be found at http://www.synopsys.com/Community/Interoperability/Pages/TapinITF.aspx

About IEEE-ISTO
IEEE-ISTO is the premier trusted partner of the global technology community for the development, adoption, and certification of industry standards. Its mission is to facilitate the life-cycle of industry standards development through a dedicated staff committed to offering vendor neutrality, quality support and member satisfaction. Fostering the market acceptance, adoption and implementation of standardized technologies, IEEE-ISTO Programs span the spectrum of today's information and communications technologies. To find out more about IEEE-ISTO, visit www.ieee-isto.org.

Add to Digg Bookmark with del.icio.us Add to Newsvine

Media Contacts 
IMTAB
Yatin Trivedi
Director, Standards & Interoperability Programs

Email Contact
+1 650 584-4423

IEEE-ISTO
Michelle Hunt
Senior Program Manager/Marketing, IEEE-ISTO

Email Contact
+1 732 981-3434 





Review Article Be the first to review this article

Aldec Simulator Evaluate Now

Featured Video
Jobs
Acoustic Systems Test Engineer for Cirrus Logic, Inc. at Austin, TX
ASIC Design Engineer for Infinera Corp at Sunnyvale, CA
RF IC Design Engineering Manager for Intel at Santa Clara, CA
Senior PIC Test Development Engineer for Infinera Corp at Sunnyvale, CA
Design Verification Engineer for Cirrus Logic, Inc. at Austin, TX
Upcoming Events
IC Open Innovation Panel During REUSE 2017 at Santa Clara Convention Center 5001 Great America Parkway Santa Clara CA - Dec 14, 2017
Essentials of Electronic Technology: A Crash Course at Columbia MD - Jan 16 - 18, 2018
Essentials of Digital Technology at MD - Feb 13 - 14, 2018
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise