Menta Unveils eFPGA Creator, Industry’s First Development Suite to Create Customizable Programmable Logic Architecture

MONTPELLIER, France — May 28, 2010 — Menta SAS, an embedded programmable logic provider of embedded-FPGA Intellectual Property (IP), today announced eFPGA Creator® the first complete development tool suite that allows designers to create customizable programmable logic architecture. By providing full control over the parameters of the embedded-FPGA structure, eFPGA Creator gives users the ability to define, build, analyze and validate the target capacity, performance, interconnect density and programming method. As part of a complete foundry-independent methodology, eFPGA Creator enables embedded-FPGA configurability for any SoC (System on Chip), on any process technology. It targets telecommunications, automotive, space and defence applications.

The eFPGA Creator suite accelerates the development of flexible SoCs with Menta‘s customizable embedded-FPGA IP products. eFPGA Creator automatically creates the eFPGA Core® IP best suited for the end application. Its Graphical User Interface (GUI) assists the designer through the definition of the tile, and core parameters such as capacity, size, aspect ratio and process constraints (technology, target performance, target power consumption).

The Generator tool automatically builds, a fully hierarchical and optimized structure, based on fully configured compact tiles. This optimized eFPGA Core IP can be customized to integrate specific hardware accelerators and functions, and designers can select the configuration storage mechanism based on the process and library availability (for example, SRAM, NVRAM or antifuse).

The Analyzer tool helps designers fine tune the best architecture parameters (LUT size, routing needs, I/Os…) for the target application.

Closely coupled with silicon flow and the Analyzer, eFPGA Creator‘s user friendly environment enables designers generate detailed performance, power and area reports, as well as all the necessary information required to embed the eFPGA Core IP into the target System on Chip (SoC).

“eFPGA Creator and Menta’s embedded-FPGA IP technology is a significant problem solver for us,” said Bruno Paucard, CEO at Scaleo Chip. “It gives us the ability to embed configurable complex programmable logic modules in our products and address one of the challenges of our market: to deliver cost effective added value features that support multiple derivatives to exactly fit with the needs of our customers.”

“With eFPGA Creator, we provide more degrees of freedom to users of our embedded-FPGA IP technology,” stated Laurent Rougé, Menta founder and CEO. “Designers retain the flexibility to retarget their designs to advanced silicon process and configure them for the best performance, area, and configurability tradeoffs.”

About Menta‘s eFPGA Core IP

Menta’s eFPGA Core IP is a programmable logic architecture IP core that leverages Menta’s proprietary ultra-compact architecture to provide the SoC designer with post-fabrication flexibility at near ASIC performance. The Menta eFPGA Core IP is customizable so a domain specific-FPGA (dsFPGA) can be used in an SoC with target applications features, and benefits in terms of area, power consumption and speed. The eFPGA Programmer® tool suite configures the core and supports the tools used to map and place and route the design.

Product availability

The eFPGA Creator development suite is now available for Linux. Please contact Menta at Email Contact for an evaluation license and pricing information.

About Menta

Menta SAS is a privately held company based in Montpellier (France). The company provides embedded-FPGA (eFPGA) technology for SoC (System on Chip), ASIC or SiP (System in Package) designs, from EDA tools to IP generation. As a result of years of research at LIRMM (Laboratory of Informatics, Microelectronics and Robotics from the University of Montpellier and CNRS), Menta’s programmable logic architecture is based on scalable, customizable, easily programmable architecture that was created to provide programmability for next generation ASIC design that incorporates the benefits of FPGA design flexibility.

For more information, visit the company website at:


Laurent Rougé
Tel.: +33 9 72 12 22 39
E-mail: Email Contact

Chantal Cochini
Tel.: +33 6 22 98 03 80
E-mail: Email Contact

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