Altos Design Automation Inc. Releases Variety MX, for Statistical Memory Characterization

New tool adopted by STARC for their STARCAD-CEL Statistical Design Flow

SAN JOSE, Calif.--( BUSINESS WIRE)-- Altos Design Automation Inc. today announced Variety MX, a fast and accurate statistical timing model generator for embedded memories. The new tool generates instance-specific Liberty® models for use by Cadence’s Encounter® Timing System GXL, Extreme DA’s Goldtimetm and Synopsys PrimeTime® VX.

Variety MX leverages technology from Liberate MX to perform “automatic probing” and "dynamic partitioning" to address the runtime and accuracy challenges that arise from statistical characterization of large macro blocks that often comprise millions of transistors. Since a “dynamic partition” represents just the active critical path for a given timing arc and is typically only a few hundred transistors, it can be characterized using similar techniques as those deployed for statistical characterization of standard cells. This includes characterizing the sensitivity of both delay and timing constraints to global (systematic) and local (random) process variations. Variety MX is able to characterize memory sizes that cannot be adequately simulated using brute Monte Carlo methods or even with fast sampling techniques.

Nobuyuki Nishiguchi, vice president and general manager at STARC said, "Our member companies are all very concerned about the impact of process variation when designing at advanced nodes and chartered STARC to develop a statistical design flow that will enable them to productively create robust, power efficient advanced SoC designs. A key missing piece in our STARCAD-CEL 3.0 flow was the ability to perform statistical timing analysis on critical paths that contain embedded memory.”

Nishiguchi continued, "We adopted Altos’ Variety MX to solve this problem because of its impressive performance that is independent of memory size. We were able to confirm that the tool’s accuracy for both delay mean and sigma satisfied our criteria perfectly when compared against Monte Carlo simulation of a complete memory instance. As often over 50% of chip area is embedded memory, we believe being able to create accurate statistical memory models in very reasonable time will greatly enhance the usefulness of any statistical design methodology.”

"STARC has been pioneering and validating the use of statistical static timing analysis (SSTA) as an improved methodology for advanced complex designs for a number of years," said Jim McCanny, Altos CEO. "We have enjoyed working with them on the deployment of our Variety standard cell statistical characterizer and are proud to have our tools adopted for the very challenging task of creating accurate SSTA models for embedded memory. STARC is widely recognized for its very detailed and thorough validation of new technology so to be included in their STARC-CEL design flow is a great endorsement of Altos’ memory characterization tool suite.”

The Variety MX Advantage

Variety MX uses “dynamic partitioning”, i.e. partitioning based on a full chip simulation of a circuit using a “fast-spice” simulator. This has the advantage of being able to account for effects common at advanced process nodes such as interconnect coupling, power supply gating and transistor stress. As “dynamic partitions” are small, they can be characterized by a “true-spice” simulator providing highly accurate results. Furthermore, without partitioning nearly all memory instances are too large to be simulated with traditional or fast Monte Carlo methods rendering statistical characterization impossible.

To account for the impact of process variation Variety MX leverages Altos’ proprietary “inside view” methods that reduce the overhead of local (random) variation characterization to 3X or less of nominal characterization, in contrast to Monte Carlo simulation which will be at least two or three orders of magnitude slower. The statistical library models generated by Variety MX are consistent with those created by Varietytm for standard cells. This includes support for statistical current source model formats, CCS VA from Synopsys and S-ECSM from Cadence.

Variety MX supports multiple “fast-spice” simulators including Synopsys CustomSim (HSIM®, NanoSim® and XA), Mentor’s ADiT and Cadence’s Virtuoso® UltraSim Full Chip Simulator for “fast-spice”. Synopsys Hspice®, Cadence’s Spectre®, Mentor’s Eldo® and Altos’ Alspice are all supported for “true-spice” simulation.


Variety MX is available now. Altos’ products are sold directly in Europe, India and North America and via distributors in Japan, Taiwan and Korea.

About Altos

Altos Design Automation provides ultra-fast, fully-automated characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization. Altos’ products support standard cells, I/Os, embedded memories and custom macros. Altos advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield.

Privately held, Altos was founded in 2005 in Santa Clara, CA. Its corporate headquarters is at 4020 Moorpark Ave., Suite 100, San Jose, CA 95117. Telephone: (408) 980-8056. On the Web at:




Altos Design Automation
Jim McCanny, 408-980-8056x103
Email Contact
Lee PR
Liz Massingill, 650-363-0142
Email Contact

Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Featured Video
Applications Engineer for intersil at Palm Bay, Florida
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Design Verification Engineer for intersil at Morrisville, North Carolina
Upcoming Events
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 26 - 29, 2018
ESC Conference Boston at boston MA - Apr 18 - 19, 2018
IEEE Women in Engineering International Leadership Conference at 150 W San Carlos St San Jose CA - May 21 - 22, 2018
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise