Verific Software Serves as Front End to Oasys Design Systems RealTime Designer

VHDL Analyzer Software Supplied by Verific to Provide Reliable Front End

ALAMEDA, Calif. — (BUSINESS WIRE) — November 17, 2009Oasys Design Systems announced today that RealTime Designer™, Chip Synthesis™ software capable of synthesizing register transfer level (RTL) code for 100-million gate designs, now includes support for VHDL through de facto standard front-end software from Verific Design Automation.

Verific licensed its VHDL analyzer to Oasys, giving RealTime Designer a common, proven and reliable front end for its unique Physical RTL synthesis. RealTime Designer is in production flows at leading-edge semiconductor and systems companies worldwide.

Verific’s software serves as the front end to numerous Field Programmable Gate Array (FPGA) and Electronic Design Automation (EDA) tools for synthesis, simulation and verification applications. The software is written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Each is licensed as source code and come with support and maintenance.

“Integrating Verific’s software with RealTime Designer had been a part of our product planning and development from the beginning because of its superior quality,” notes Paul van Besouw, president and chief executive officer of Oasys. “Verific’s customer support group has a reputation for outstanding service and each member lived up to that reputation.”

“Oasys’ RealTime Designer has the potential to be a game-changing EDA tool,” says Michiel Ligthart, Verific’s chief operating officer. “Anytime one can reduce logic synthesis and optimization runtime by a factor of 10 it will get noticed by the user community.”

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, is a leading provider of SystemVerilog, Verilog and VHDL front-end software founded in 1999 by EDA industry veteran Rob Dekker. Verific’s software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: www.verific.com.

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.



Contact:

Public Relations for Verific
Nanette Collins, 617-437-1822
Email Contact




Review Article Be the first to review this article

Aldec Simulator Evaluate Now

Featured Video
Jobs
Principal PIC Hardware Controls Engineer for Infinera Corp at Sunnyvale, CA
ASIC Design Engineer for Infinera Corp at Sunnyvale, CA
Senior PIC Test Development Engineer for Infinera Corp at Sunnyvale, CA
Senior DSP Firmware Engineer for Cirrus Logic, Inc. at Austin, TX
Design Verification Engineer for Cirrus Logic, Inc. at Austin, TX
Senior Formal FAE Location OPEN for EDA Careers at San Jose or Anywhere, CA
Upcoming Events
IC Open Innovation Panel During REUSE 2017 at Santa Clara Convention Center 5001 Great America Parkway Santa Clara CA - Dec 14, 2017
Essentials of Electronic Technology: A Crash Course at Columbia MD - Jan 16 - 18, 2018
Essentials of Digital Technology at MD - Feb 13 - 14, 2018
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise