Satin IP to Participate in Panel on Improving IP Quality vs. Losing Design Productivity at IP-ESC Conference

MONTPELLIER, France – November 19, 2009 – Satin IP Technologies, the company that delivers design quality closure with fast return on investment, will participate in a panel to discuss improving intellectual property (IP) quality without losing design productivity at the IP-Embedded Systems Conference in Grenoble, France on December 1, 2009.

What:  The panel -- entitled “Improving IP Quality vs. Losing Design Productivity – What Are the Tradeoffs?” -- will discuss issues that arise when time-to-market and cost reductions dominate IP design and integration, since instituting design practices for enhanced quality can be seen as overhead by engineers and engineering managers. This panel will use real world examples from IP buyers and sellers to address questions like: How do you balance the cost of addressing IP quality up front vs. after tape-out ? Where do semiconductor companies and IP vendors usually set the cursor? What are the most important quality issues to address? How helpful are the quality standards in addressing key issues? Is there any way to reduce the impact of quality management on design schedules and costs?

Who: Panel chairperson is Phil Dworsky, Director of Strategic Alliances at Synopsys

Panelists are:

  • Philippe Di Crescenzo, Director of Engineering, Arteris
  • Kathryn Kranen, President and CEO, Jasper Design Automation
  • Joachim Kunkel, Vice President and General Manager, Solutions Group, Synopsys
  • François Rémond, CAD & Design Methodology Director, STMicroelectronics
  • Michel Tabusse, President and CEO, Satin IP Technologies


When: Tuesday, December 1, 2009 from 17:15 to 18:45


Where: In the auditorium at the IP-Embedded Systems Conference in the World Trade Center in Grenoble, France


For additional information, please see


About Satin IP Technologies

Committed to design quality closure with fast return on investment (ROI), Satin IP Technologies delivers software solutions for fact-based design quality monitoring. Working within customers' design flows, VIP Lane® turns customers' design practices for IP blocks or SoCs into a robust set of quality criteria and automates the implementation and documentation of design quality metrics at no extra cost in engineering time or resources. VIP Lane shortens time-to-market by delivering effective flow integration and on-the-fly quality monitoring at zero overhead to design teams. Satin IP is a privately-held company with headquarters in Montpellier, France. For more information, see


VIP Lane® is a registered trademark of Satin IP Technologies. All other product or service names are the property of their respective owners. All rights reserved.


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Media Contacts:

Linda Marchant, Cayenne Communication (USA),  919-451-0776,

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