Dr. Pranav Ashar, Real Intent's CTO, will speak about "Improving Verification Efficiency with Rule Based Automatic Formal Analysis" at the 7th annual International System-on-Chip Conference in Newport Beach, California.
Real Intent, Inc. is known as the innovator in automating the intelligence of formal technologies for electronic design verification.
Dr. Pranav Ashar rejoined Real Intent this year and previously served as the company's CTO from 2004 to 2006. He previously worked at NEC Labs (Princeton, NJ) developing formal verification technologies for VLSI design. He authored about 70 papers and co-authored a book titled "Sequential Logic Synthesis." He holds a Ph.D. in EECS from UC Berkeley.
Improving Verification Efficiency with Rule-Based Automatic Formal Analysis
The cost of functional verification is a dominant contributor to SOC design costs. It is therefore desirable to improve the efficiency of functional verification so as to reduce cost. This presentation discusses rule-based automatic formal analysis as the opportunity for improving verification efficiency.
1:30-2pm, Thursday, November 5, 2009
Newport Beach, California
Information and Registration
For more information about Real Intent, please visit www.realintent.com.
About Real Intent
Real Intent is the leading innovator in automating formal techniques for design verification. This technology is being used in the field today to solve critical problems encountered by design and verification teams worldwide. Real Intent's family of products dramatically improves the functional verification efficiency of leading edge ASIC and FPGA based designs.
Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: +1 (408) 830-0700 fax: +1 (408) 737-1962, Web: www.realintent.com, e-mail: Email Contact, Twitter: www.twitter.com/RealIntent.
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