"The Cadence methodology for UMC's 40-nanometer process allows designers to create power-efficient chips using a single methodology that delivers consistent power intent all the way to production," said Stephen Fu, director of the IP Development & Design Support Division at UMC. "In addition, the flow supports the UMC 40-nanometer process with advanced design-side DFM capabilities during physical implementation for lower risk and faster time to volume."
The UMC reference flow employs the CPF-enabled Encounter® Digital Implementation (EDI) System and Cadence Low-Power Solution, and is aimed at efficient energy use and highest yield for 40-nm system-on-chip designs. The Cadence Low-Power Solution is the industry's first complete flow that integrates logic design, verification, and implementation with the Si2-standard Common Power Format and features power awareness throughout all necessary design steps, including logic synthesis, simulation, design for test, equivalence checking, silicon virtual prototyping, physical implementation and complete signoff analysis. CPF is an Si2-approved industry standard format for specifying power-saving techniques early in the design process, enabling sharing and reuse of low-power intelligence.
In addition to low power, the UMC reference flow also employs the Encounter Digital Implementation System's full suite of integrated and foundry-certified model-based DFM capabilities for lithography. This enables designers to confidently prevent, analyze, and optimize for potential DFM hot-spots during the physical implementation flow in concert with other optimizations, including timing, signal integrity, area, power, and yield.
"The Cadence Low-Power Solution is unique, and our integrated DFM technologies are essential to advanced design methodologies today," said Nitin Deo, group marketing director of Implementation Products at Cadence. "We are proud of our collaboration with UMC to provide the industry with a robust 40-nanometer design flow that delivers the most important requirements for designs today: performance, power efficiency, productivity, reliability and superior manufacturability."
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Cadence, the Cadence logo, and Encounter are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact: Dan Holden Cadence Design Systems, Inc. 408-944-7457 Email Contact