Azuro Strengthens Leadership in Low-Power CTS on Complex SoC Designs

SANTA CLARA, Calif. — (BUSINESS WIRE) — July 28, 2009 Azuro, Inc., a provider of advanced implementation tools for nanometer chip design, today announced version 5 of its PowerCentric™ low-power clock tree synthesis (CTS) solution with extended support for complex system-on-chip (SoC) designs.

“Azuro’s proprietary global approaches to clock tree balancing and patented clock gate optimization algorithms are ideally suited to complex SoC designs,” said Paul Cunningham, CEO and co-founder of Azuro. “PowerCentric is being actively used to tape out many of the world’s most complex chips with hundreds of intertwined clocks and dozens of voltage islands. This latest software release strengthens our proven leadership position in CTS and reinforces Azuro’s continued commitment to deliver lowest clock power, best clock gate timing, and fastest CTS turnaround time.”

Key features in PowerCentric version 5 include:

  • 30% reduction in CTS runtimes on designs with multiple modes and corners.
  • Enhanced clock gate optimization and clock tree buffering algorithms delivering up to 10% additional clock power savings.
  • Comprehensive support for UPF 2.0 (IEEE 1801™) power domain configuration format.
  • Ground breaking new “Trial CTS” capability delivering accurate post-CTS design timing with runtimes of less than one hour per one million placeable instances.
  • Top level clock balancing through hardened sub-chips with back-annotated parasitics.
  • Full database save with rapid restore.

PowerCentric version 5 is available now with UPF 2.0 support in limited availability. For more information on Azuro’s products and the technology behind them, please visit www.azuro.com.

About PowerCentric™

PowerCentric is a complete replacement for the clock tree synthesis (CTS) step in a digital chip design flow. It reduces chip power by up to 20% and dramatically increases designer productivity on designs with complex clock networks.

About Azuro™

Azuro is an electronic design automation (EDA) company supplying software tools to design digital semiconductor chips. The company’s unique clock tree synthesis and physical optimization technologies make chips faster, reduce chip power and dramatically accelerate chip time to market. Customers of Azuro’s software include Broadcom, Cambridge Silicon Radio, NVIDIA, NXP, STMicroelectronics, and Texas Instruments. Founded in 2002, the company is headquartered in Santa Clara, CA with R&D in Cambridge, UK, and is privately held.

Rubix, SASim, and PowerCentric are trademarks of Azuro, Inc.



Contact:

Azuro, Inc.
Marc Swinnen, 408-464-7350
Email Contact
or
Cayenne Communication
Linda Marchant, 919-451-0776
Email Contact




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