Azuro's Clock Tree Synthesis Solution Used by STMicroelectronics to Tape Out Set-Top Box Design
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Azuro's Clock Tree Synthesis Solution Used by STMicroelectronics to Tape Out Set-Top Box Design

Azuro's PowerCentric improves clock timing and shortens design time

SANTA CLARA, Calif., July 21, 2009 - Azuro, Inc., a provider of advanced implementation tools for nanometer chip design, announced today that STMicroelectronics' Home Entertainment and Displays (HED) Group has successfully taped out its next-generation Set-Top Box (STB) chip using Azuro's PowerCentric™ clock tree synthesis solution. ST was able to quickly deploy PowerCentric within their chip implementation flow to significantly improve clock timing while also reducing clock area.

"Azuro reduced the insertion delay of our critical clocks by 15% which allowed us to meet our performance targets," said Francois Remond, Director of CAD & Design Methodology for the HED group at STMicroelectronics. "PowerCentric's superior results and unique graphical analysis capabilities also allowed us to quickly identify bottlenecks and accelerate our clock implementation process."

ST's advanced 65nm system-on-chip (SoC) designs have multiple interleaved clock domains with numerous logic paths crossing between domains. This makes insertion delays of clocks a critical factor in achieving the timing goals for the design. The sophistication of ST's design is also reflected in the complexity of its clocking scheme. Rising clock complexity can add significant delay to the chip design process unless automation tools like PowerCentric are adopted that can deal with this level of complexity.

Paul Cunningham, co-founder and chief executive officer for Azuro said, "Clock timing is becoming a top design issue as we experience a sharp increase in the number and complexity of clocks on SoC designs. It was a pleasure to work with the ST design team, which quickly applied Azuro's technology to a large complex design, and we look forward to continuing our close cooperation."

About Azuro
Azuro is an electronic design automation (EDA) company supplying software tools to design digital semiconductor chips. The company's unique clock tree synthesis and physical optimization technologies make chips faster, reduce chip power and dramatically accelerate chip time to market. Customers of Azuro's software include Broadcom, Cambridge Silicon Radio, NVIDIA, NXP, STMicroelectronics, and Texas Instruments. Founded in 2002, the company is headquartered in Santa Clara, CA with R&D in Cambridge, UK, and is privately held. Rubix and PowerCentric are trademarks of Azuro, Inc.

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Keywords: clock tree synthesis, low power, chip, integrated circuit, IC, electronic design automation, EDA, PowerCentric, Azuro, power analysis, average power, battery life, circuit activity, dynamic power, leakage power

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