Solido Design Launches New Process Variation Solution to Solve Well Proximity Effect Problems for Sub-90 nm Analog Designs

SAN JOSE, Calif. — (BUSINESS WIRE) — June 23, 2009 Solido Design Automation, a leading developer of software for eliminating design loss caused by process variation in analog/mixed-signal and custom integrated circuits, today announced the availability of a new application for its Variation Designer solution that analyzes and solves well proximity effect problems that become major concerns at 90 nm and below. The new Solve Well Proximity application allows semiconductor designers to avoid heuristics-based conservative guard-banding or multiple iterations between circuit and layout. Instead, designers are able to proactively address well proximity effects during the circuit-design stage without area sacrifices or increased design time resulting from other approaches. For example, in a 90 nm power management system amplifier design, guard-banding area was reduced by 95 percent compared to the traditional methodology. Similarly, the design and layout time for a 65 nm high-speed display driver was reduced from 2 weeks to 1.5 days.

Solve Well Proximity is the first of Solido’s applications that is targeted specifically at systematic proximity variation effects, and extends the company’s current portfolio of statistical variation applications available for Variation Designer, a scalable and extensible platform introduced earlier this year. Users will be able to plug the new application into Variation Designer without the need for re-integration with their design flows.

“As processes migrate to smaller geometries, new process variation effects play a bigger role in the performance of circuits,” said Amit Gupta, President and CEO of Solido Design Automation. “The industry is interested in these variation issues because they impact the ability to realize the benefits of migrating to new technologies. Not properly accounting for process variation effects results in increased costs and time to market, and decreased chip performance. Adding the Solve Well Proximity application to our portfolio allows us to continue building the widest ranging, most comprehensive set of solutions to process variation problems.”

About the Solve Well Proximity Application

Well proximity effects occur because, during the CMOS manufacturing process, atoms can scatter laterally from the edge of the photoresist mask and become embedded in the silicon surface near the edges of the retrograde wells needed for latch-up protection and suppression of lateral punch-through. This causes the MOSFET electrical characteristics to vary with the distance of the transistor from the well-edge. Traditionally, there have been two ways to deal with proximity effects. In one, because it is not known at the circuit design stage which devices are sensitive to the effects, the designer uses heuristics to conservatively guard-band devices. This results in area penalties. In the other approach, the circuit designer obtains post-layout extracted netlists and simulates to determine if there are any proximity effect-related issues. This is an iterative process and results in design time penalties.

The Solve Well Proximity application leverages foundry-provided well proximity parameters that are included in the SPICE model files but are not normally used due to the lack of appropriate tools at the circuit design stage. The new application is used by a chip designer during the circuit design stage to proactively account for well proximity effects. The designer can determine which devices are sensitive to proximity effects and by how much, and can obtain the appropriate proximity parameter values and minimum well distances. These values are back-annotated into the schematic and are then used by the layout engineer, reducing the silicon area occupied by excessive guard-banding and eliminating the time consumed by iterative post-layout simulations.


The Solve Well Proximity application is now available for use with the Variation Designer platform, and will be demonstrated in the Solido booth (number 3060) at the DAC (Design Automation Conference) in San Francisco, July 27 – July 30, 2009.

DAC Demonstration

In its booth (number 3060) at the DAC, Solido Design Automation will be highlighting Variation Designer, the first scalable and extensible solution for eliminating design loss caused by process variation in analog/mixed-signal and custom integrated circuits. With Variation Designer, Solido will be demonstrating its statistical applications, which utilize PVT (process, voltage, temperature) corners and/or design-specific True Corners to account for global, local and environmental variation. It will also demonstrate the new Solve Well Proximity application, which enables designers to proactively solve for well proximity effects at the circuit design stage, saving design time and reducing area.

About Solido Design Automation

Solido Design Automation Inc. provides software for eliminating design loss caused by process variation in analog/mixed-signal and custom integrated circuits. The privately held company is venture capital funded and has offices in the U.S.A., Canada, Japan and Europe. For further information, visit or call 306-382-4100.


Cayenne Communication LLC for Solido Design Automation
Michelle Clancy, 252-940-0981 (PR)
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