|Jasper’s new Proof Accelerators are:|
|Formal Scoreboard™ 2|
|The latest version of Formal Scoreboard is used to prove the integrity of data transfers across a design. Its multiple input and output ports make it possible to verify many different types of data transfers, such as transfers relying on byte enables and bus-width conversion, or serial-to-parallel conversion. To further improve performance and usability, Formal Scoreboard 2 has an updated and more versatile user interface.|
|Model RAM makes memories tractable, providing a means of achieving full, unbounded proofs on properties that involve logic containing memories. It achieves this goal by providing a flexible abstraction that enables the formal engines to abstract the majority of the specified memory while preserving those parts of its behavior that are needed to achieve the proof.|
|Multiplier verification can affect the state-space of a design, but this component provides a “formal safe” method for modeling multipliers ideally suited for complex designs such as DSPs and graphics/video/network processors.|
Proof Accelerators & JasperGold
JasperGold provides rapid bug detection and debug as well as end-to-end full proofs of expected design behavior, and provides valuable insight across the design cycle in architectural analysis, RTL debug, verification and post silicon debug. Jasper’s Proof Accelerators speed up formal proofs to significantly reduce verification complexity, and combined with Design Tunneling™ can consistently perform full proofs on properties where other formal tools fail to converge, with an average 10x proof capacity advantage over competitors.
A selection of Proof Accelerators for JasperGold are currently available to handle myriad applications, including data transfer integrity, FIFO and memory modeling, data synchronization across clock domains, cache verification, and more. For complete details contact Jasper at: Email Contact.
About Jasper Design Automation
Jasper delivers industry-leading EDA solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 100 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, India and Japan. Visit www.jasper-da.com for Targeted ROI: reducing risks; increasing design, verification and reuse productivity; and accelerating time to market.
Jasper Design Automation, the Jasper Design Automation logo, ActiveDesign, Behavioral Indexing, and JasperGold are trademarks or registered trademarks of Jasper Design Automation, Inc. All other trademarks mentioned are the property of their respective companies.
lochpr for Jasper Design Automation
Jim Lochmiller, 707-205-7681