Jasper Extends Formal Verification Technology Lead With Four New Patents in Portfolio

MOUNTAIN VIEW, Calif.—(BUSINESS WIRE)—March 25, 2009— Jasper Design Automation, provider of advanced formal technology solutions, today announced it has been awarded four new U.S. patents. The recent patents further advance the company’s formal technology, according to Jasper CTO Rajeev Ranjan. “Jasper’s commitment to core formal research produces products that enable our customers to achieve design closure faster, and with greater confidence,” he said. “Our R&D continues to deliver verification innovation at all stages of the design, to heighten quality and productivity throughout the flow, from architecture to production.”

The new patents cover a variety of innovations:

  • 7,437,694 - Identification of certain RTL load signals and values, with their contribution to the proof target. This targeted information enables high performance and fast comprehension for formal users.
  • 7,421,668 - Meaningful visualization of properties independent of a circuit design under various conditions, which helps users debug any errors in how the property is implemented in a requirements model.
  • 7,418,678 - This invention provides methods for simplifying counters in a circuit design while preserving important implications, enabling reliable verification of circuit designs that use counters.
  • 7,412,674 - Applies the concept of analysis regions to analyze the properties/requirements for a design. This generates a visual display that is available to the user, representing source code in the analysis region for properties in comparison to the maximum possible analysis region.

Jasper has now been granted 11 patents, with additional patents pending. Through continuous innovation and responsiveness to market-driven requirements, Jasper delivers proven “Targeted ROI” to customers by solving their most critical design challenges in ways that also speed time to market, reduce overhead, and mitigate risk. This philosophy is embodied in JasperGold®, the industry’s most powerful and effective deep formal verification solution; and ActiveDesign™ with Behavioral Indexing™ for accelerated legacy design and IP comprehension and reuse.

About Jasper Design Automation

Jasper delivers industry-leading EDA solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 100 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, India and Japan. Visit www.jasper-da.com for Targeted ROI: reducing risks; increasing design, verification and reuse productivity; and accelerating time to market.

Jasper Design Automation, the Jasper Design Automation logo, ActiveDesign, Behavioral Indexing, and JasperGold are trademarks or registered trademarks of Jasper Design Automation, Inc. All other trademarks mentioned are the property of their respective companies.



Contact:

lochpr for Jasper Design Automation
Jim Lochmiller, 707-205-7681
Email Contact




Review Article Be the first to review this article
CST: Webinar October 19, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Upcoming Events
Preparing for the Cognitive Era: Education, Occupation and You at SJSU Student Union Theater 211 South 9th Street San Jose CA - Oct 18, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
15th IEEE/ACM ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise