“Clock concurrent optimization makes sense. Rubix plugged easily into our flow, and improved key chip speed metrics (WNS and TNS) out of the box on some of our toughest blocks, with no impact on area,” said David Dumolin, director engineering at NVIDIA. “We view clock concurrent optimization as a key evolutionary step in backend physical design.”
Physical optimization is the step in the design flow which most influences chip speed, area, and power. But physical optimization occurs before clocks are inserted into a design during the clock tree synthesis step and makes decisions based on an idealized, balanced model of clocks. At 65nm and below, this model has diverged dramatically from reality due to three key industry trends: design complexity, on-chip-variation, and low power. This divergence directly impacts the validity of decisions made during physical optimization, significantly degrading achievable chip speed and causing a dramatic spike in manual iterations in design flows. Clock concurrent optimization addresses this divergence by building clocks during—rather than after—physical optimization and therefore makes all decisions based on real clocks, not idealized clocks.
“Clock gating, on-chip variation, and an explosion in inter-clock timing complexity collectively cripple the ability of traditional physical optimization tools to perform timing optimization effectively,” said Greg Buchner, former vice president engineering at ATI Technologies and AMD, and an advisor to Azuro. “Clock concurrent optimization truly is something fresh and much needed by the chip design community.”
Commenting on clock concurrent optimization, EDA industry analyst, Gary Smith, chief analyst at GSEDA added, “Traditional clock tree synthesis died at 65nm. Merging clock tree synthesis and physical optimization makes total sense to me.”
Using an idealized, balanced model of clocking, the time available for logic functions between registers is assumed to be equal, and chip speed is therefore limited by whichever logic function on a chip is slowest. Since clock concurrent optimization builds clocks simultaneously with optimizing logic, the time available for logic functions need not be the same and can be varied by individually controlling when clock signals arrive at registers. Using clock concurrent optimization, chip speed becomes limited by whichever “chain” of logic functions is slowest, where these chains break only when they reach an input to, or an output from, a chip or when they loop back on themselves. It is the explicit minimization of critical logic chains, as opposed to critical logic paths, which most differentiates clock concurrent optimization from traditional physical optimization.
“Neither the RTL coding languages used to design chips nor the verification tools used to sign off on final chip layouts requires that clocks be balanced,” said Steve Teig, former CTO of Cadence Design Systems. “Since idealized clocks no longer match reality, giving up on the idea of balancing is a true win-win: timing optimization can be based on real clocks, and the lack of any requirement to balance clocks unleashes significant new freedoms to increase chip speed.”
Commenting on Rubix, Paul Cunningham, Azuro’s co-founder and CEO said, “Clock concurrent optimization is the right way to address the crippling pre- to post-CTS timing gap which has emerged in design flows today. We feel privileged to be able to introduce a technology concept as fundamental as clock concurrent optimization, and look forward to helping chip design teams exploit the significant benefits Rubix can offer to their businesses.”
Rubix leverages the same flow integration interface used by PowerCentric™, Azuro’s widely adopted CTS solution. Rubix is in limited availability to select Azuro customers, with general availability scheduled for April.
For more information on clock concurrent optimization, please see the “Clock Concurrent Optimization” white paper at http://www.azuro.com/rubix/white-paper.html
Azuro is an electronic design automation (EDA) company supplying software tools to design digital semiconductor chips. The company’s unique clock tree synthesis and physical optimization technologies make chips faster, reduce chip power and dramatically accelerate chip time to market. Customers of Azuro’s software include Broadcom, Cambridge Silicon Radio, NVIDIA, ST Microelectronics, and Texas Instruments. The company was founded in 2002, and has completed over 40 tapeouts since launching its first product in 2005. Azuro is headquartered in Santa Clara, CA with R&D in Cambridge, UK, and is privately held.
Rubix and PowerCentric are trademarks of Azuro, Inc.
Keywords: clock tree synthesis, physical optimization, timing optimization, clock concurrent optimization, design complexity, ideal clock, propagated clock, useful skew, skew, on-chip variation, low power, semiconductor, integrated circuit, IC, electronic design automation, EDA, RTL
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