Reminder - Accellera Announces Call for Nominations for 2009 Annual Technical Excellence Award Honoring Contributions to Electronic Design Automation Standards

NAPA, CA -- (MARKET WIRE) -- Jan 05, 2009 --


Who/What:

Accellera, the electronics industry organization focused on Electronic Design Automation (EDA) standards, invites the electronic design community to nominate an individual for its 6th annual Technical Excellence Award. Accellera's Technical Excellence Award recognizes the outstanding achievements of its Technical Subcommittee members in creating electronic design standards that benefit the EDA, semiconductor, intellectual property (IP) and electronic systems industries.

Accellera provides a framework that enables the technical work of its committees, logistics and the infrastructure for obtaining and distributing funds and resources for EDA standards, that when approved are available to everyone in the electronics community at no cost.

When/Where

Accellera's Technical Excellence Award nominations are due Friday, January 9, 2009. Accellera's Technical Excellence Award will be presented during Accellera's Design Verification Conference (DVCon), February 24-26, 2009, at the Doubletree Hotel in San Jose.

Information

For more information about Accellera and its EDA standards please visit www.accellera.org. To nominate an individual, please visit http://www.accellera.org/activities/award/. For more information about DVCon, please visit www.dvcon.org.

About Accellera's Technical Subcommittees

Accellera's Technical Subcommittees produce effective and efficient standards for today's advanced IC designs. Participation comes from Accellera member companies, industry contributors, and independents. Technical contributors typically have many years of practical experience with IC design and developing and using design automation tools.

Accellera's Technical Subcommittees include: Interface (ITC), Open Compression Interface (OCI), Open Verification Language (OVL), Property Specification Standard (PSL), SystemVerilog, Unified Coverage Interoperability (UCI), Unified Power Format (UPF), Verilog Analog/Mixed-Signal (Verilog-AMS), Verification Intellectual Property (VIP) and VHDL. More information is at www.accellera.org.

About Accellera's IEEE Electronic Design Standards

Accellera has transferred its completed standards work to the IEEE and continues to use this strategy as part of the roadmap for all of its standards.

To date, seven Accellera EDA standards have been ratified by the IEEE -- Hardware Description Language (HDL) standards, Verilog or IEEE 1364, VHDL or IEEE1076, Property Specification Language (PSL) or IEEE 1850 and SystemVerilog or IEEE 1800; Standard Delay Format (SDF) or IEEE 1497; Delay and Power Calculation System (DPCS) or IEEE 1481 and Advanced Library Format (ALF) or IEEE 1603. In addition, two standards are active in IEEE Working Groups, Open Compression Interface (OCI) or IEEE 1718 and Unified Power Format (UPF) or IEEE P1801. Accellera's most recent advanced design and verification language standards include the SystemVerilog and the PSL standards.

About Accellera

Accellera provides design and verification standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA standards that lower the cost of designing commercial IC and EDA products. As a result of Accellera's partnership with the IEEE, Accellera standards are provided to the IEEE Standards Association for formalization and ongoing change control. For more information about Accellera, please visit www.accellera.org.

Notes to Editors:

Acronyms and Abbreviations
ALF   Advanced Library Format
AMS   Analog, Mixed Signal
DPCS  Delay and Power Calculation System
EDA   Electronic Design Automation
HDL   Hardware Description Language
IC    Integrated Circuit
IEEE  Institute of Electrical and Electronics Engineers
OCI   Open Compression Interface
PSL   Property Specification Language
SDF   Standard Delay Format
Std.  Standard
UPF   Unified Power Format
VHDL  Very High-Speed IC (VHSIC) HDL

All trademarks and tradenames are the property of their respective owners.

Press Contact:
Georgia Marszalek
ValleyPR for Accellera
+ (650) 345-7477

Email Contact





Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Upcoming Events
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
ARM TechCon 2017 at Santa Clara Convention Center Santa Clara CA - Oct 24 - 26, 2017
MIPI DevCon Bangalore 2017 at The Leela Palace Bengaluru India - Oct 27, 2017
MIPI DevCon Hsinchu City 2017 at Sheraton Hsinchu Hotel Taiwan - Oct 31, 2017
CST: Webinar series
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise