IMEC Newsletter 53 – July 2008
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IMEC Newsletter 53 – July 2008

INDEX

Editorial
Technology reports

Novel organic light-emitting device: hybrid between LED and FET
Wafer-thinning for 3D chip stacking: sub-surface damage model of roughly and ultra-finely ground Si wafers
ECG delineator algorithm extends wireless ECG patch
IMEC characterizes leakage current and anneal-induced defect creation in SiGe source/drain junctions
IMEC helps set agenda for ESD protection of next-generation devices
IMEC reduces cost of double patterning lithography
IMEC develops proof-of-concept microfabricated probes for deep brain stimulation and recording
New promising method to fabricate ultra-thin crystalline Si wafers for solar cells

Newsflashes
IMEC board reports successful 2007
IMEC and AIXTRON set important step towards low-cost GaN power devices
IMEC’s >100Mbps SDR baseband chip functional
Holst Centre opens roll-to-roll research line for printed electronics
IMEC reports progress on simplified high-k/metal gate process for the 32nm node
IMEC completes acceptance of ASML’s extreme ultraviolet Alpha Demo Tool

Industry link
Renesas collaborates with IMEC on reconfigurable RF transceivers
Singulus Mastering and Bekaert extend and expand participation in Holst Centre

FutureFab

Patents
Courses
Awards
Events
Colophon


Editorial

The first technology to drop out of the race for the next generation of lithography tools is known. High-index immersion lithography, which uses non-water fluids between the optical lens and the wafer, was originally earmarked to push 193nm immersion lithography towards the 32nm node. However, the development kept lagging behind the roadmap, and the industry was losing confidence in this technology. Nikon recently confirmed this at the 2008 Litho Forum - where the readiness of the various advanced-node lithography candidates was discussed. 1.35NA water-based immersion lithography will now be pushed to its limits for the production of advanced integrated circuits.

Double patterning and extreme-ultraviolet (EUV) remain as the two lithography options for the 32 and 22nm technology nodes. During the 2008 Litho Forum, the lithography community concluded that double patterning will be the primary candidate for the 32nm half pitch in the beginning of the next decade. Double patterning will thus close the gap between immersion lithography and EUV lithography, with EUV taking over in the middle of the next decade for the 22nm half pitch. Several double patterning approaches, using the existing 193nm immersion toolset, offer a solution for the 32nm half pitch. However, all double patterning schemes add extra process steps and extra costs. Therefore, the priority of IMEC’s advanced lithography program on double patterning is to assess the feasibility of novel, cost-effective processes, and to validate the most promising ones in terms of defectivity, implementation, controllability etc. As an example, the development of JSR Corporation’s freezing material for a double-exposure/single-etch process shows very promising results for mass production processes.

With the high-index route set aside, the question now is if double patterning with 193nm immersion lithography can be pushed to the 22nm half pitch node. The need to do this will largely depend on the readiness of EUV in 2014-2015. On this note, IMEC confirms that it has finished the site acceptance tests for ASML’s Alpha-Demo EUV tool and that it has successfully patterned the contact level of a 32nm SRAM cell using EUV.

We have gained momentum in EUV over the past 6 months. But there still are some important bottlenecks to overcome. Most importantly, the sources of EUV radiation explored today do not yet produce sufficient power. Secondly, the use of state-of-the-art resists seems limited to 32nm. For smaller features, it is difficult to optimize resolution, sensitivity and line-edge roughness all together. And thirdly, EUV appears vulnerable to much smaller mask defects than 193nm lithography. In view of these concerns, the industry will most likely not have an early EUV production tool for the 32nm half pitch node. But, stimulated by recent progress and with a concerted effort from all actors involved, we will advance EUV full speed towards the 22nm node.

As an important aside, the logic companies have started to demand more and more R&D in the field of e-beam maskless lithography. Maskless lithography (M2) is a potential solution for advanced logic devices that typically have low mask utilization and therefore suffer from the high mask costs associated with mask-based lithography. The development of maskless e-beam equipment has only just started, and there is a growing demand for preparatory research on the types of resists, and on the pros and contras of the technique. Within IMEC’s advanced lithography program, we are currently delineating an appropriate strategy to tackle this little-explored domain.

Kurt Ronse, IMEC Lithography Department Director

Technology report

Novel organic light-emitting device: hybrid between LED and FET

IMEC reports the development of an organic light-emitting device that is a hybrid between a diode and a field-effect transistor (FET). Its high current density (corresponding to a hole current density in the order of 10Acm-2) in combination with reduced optical absorption losses may lead to interesting applications such as waveguide organic light-emitting diodes (OLEDs) and possibly a laser structure.

In conventional OLEDs, the current is typically limited by the low mobility of the charge carriers in the organic semiconductor layer. Charge transport occurs perpendicularly to the organic layers, and this limits the total thickness of the layers to 80-100nm. As a consequence, light is generated very close to the metallic cathode (approx. 50nm). This induces severe absorption losses if the OLED is used as a waveguide. Recently, light-emitting organic field-effect transistors (LEOFETs) have been proposed as an alternative device. These three-electrode structures combine the optical output of an OLED and the gate control of an OFET in one single device. The charge transport occurs in the plane and the carriers are transported by field-effect. The field-effect mobility can be several orders of magnitude higher than the charge carrier mobility in a conventional OLED. However, the field-effect materials that are used in such structures usually show a rather weak photoluminescence.

To solve the drawbacks of both OLEDs and LEOFETs, IMEC proposes a novel two-electrode light-emitting device that incorporates aspects of both a diode and a FET. Compared to conventional OLEDs, the cathode is displaced by one to several micrometers from the light-emitting zone. The micrometer-sized distance between the cathode and the active region can be bridged by electrons with enhanced field-effect mobility. As a result, this heterojunction device allows minimizing optical losses at the metal cathode. Since the light-emission zone is not covered by metal, the device can be used for top emission, or even as a waveguide.

The device has been fabricated using poly(triarylamine) (PTAA) as the hole-transport material, tris(8-hydroxyquinoline) aluminum (Alq3) doped with 4-(dicyanomethylene)-2-methyl-6-(julolindin-4-yl-vinyl)-4H-pyran (DCM2) as the active light-emitting layer, and N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (PTCDI-C13H27), as the electron-transport material.

The fabricated device emits red light originating from the light-emitting layer DCM2. Light emission always occurs at a fixed position (near the edge of the insulator), irrespective of the applied bias. In LEOFETs, when the electron and hole mobilities differ significantly, the position of the recombination region is sensitive to the biasing conditions, which makes it hard to confine the light-emitting region in the middle of the channel; the excitons are almost certainly quenched, either by the source or by the drain electrode. In the new light-emitting device, light emission occurs always at a large distance of the metallic contact even when the hole and electron mobility differ significantly.

The external quantum efficiency (max. 0.02%) has been confirmed to be as high as in a conventional OLED using the same materials. The quantum efficiencies are remarkably current-independent up to current densities of more than 10Acm-2. And the light intensity can be tuned by changing the distance between the metallic contact and the insulator edge. These properties may be useful for the future fabrication of solid-state high-brightness organic light sources.

[Figure OLED-1 Schematic architecture of the OLED exhibiting field-effect electron transport.]

[Figure OLED-2 (Left panel) optical microscopy reflection image of a device without bias. The white area is the reflective metal cathode; the arrow indicates the insulator edge. (Right panel) optical microscopy image under forward bias. A narrow line of light appears along the insulator edge. The width of the line is estimated to be about 2µm.]

NOTE
This work has appeared in the March 2008 edition of Laser Focus World. More details can be found in Advanced Functional Materials 2008, 18, 136-144.

News from IMEC’s (sub-)32nm research platform

Technology report

Wafer-thinning for 3D chip stacking: sub-surface damage model of roughly and ultra-finely ground Si wafers

Based on micro-Raman spectroscopy measurements, IMEC has identified and modeled the structure of the sub-surface damage induced by the rough and ultra-fine mechanical grinding steps that are used to make ultra-thin Si wafers. These results are important for the fabrication of ultra-thin wafers used in e.g. three-dimensional chip stacking.

Mechanical grinding is the most cost-effective method to reduce the thickness of a Si wafer to less than 50µm. Such ultra-thin Si wafers are gaining importance in various application areas such as three-dimensional chip stacking, advanced flexible packaging and micro-electromechanical systems. But mechanical grinding, which uses a diamond grit wheel to remove Si, causes damage to the wafer surface. This damage may have an impact on the mechanical properties of the wafer as well as on the electrical characteristics of the integrated circuits. Until now, the fundamental nature of this damage was not well understood.

IMEC has used micro-Raman spectroscopy (µ-RS), in combination with other characterization techniques, to investigate the damage induced by rough and ultra-fine mechanical grinding. Full thickness 200mm (100) Si wafers were first ground down to 625µm. The rough grinding (RG) was performed on the (100) plane using a 320 mesh diamond grit wheel. On some of the roughly ground wafers, ultra-fine grinding was done using Disco Poligrind (PG).

Based on the µ-RS measurements, the damage and its distribution have been summarized into multilayer damage models of both PG and RG Si wafers. The PG model shows a uniform layer build-up, consisting of amorphous-Si (a-Si) (a few nanometers), plastically deformed Si (~2µm), elastically stressed Si (~2µm), and damage-free Si. In RG-Si, a similar structure is shown, however with much thicker layers (a-Si~70µm, plastically deformed Si~3.5µm, elastically stressed Si~20µm). The residual stress after rough and ultra-fine grinding is in the range of several hundreds MPa and 30MPa, respectively.

The amorphous layer is the result of sequential phase transformations, from Si-I, over Si-II, to a-Si, under the grinding conditions. Its thickness is influenced by the grinding load, which is much higher for rough grinding. These phase transformations correspond to a ductile grinding mechanism, which is dominating in ultra-fine grinding. On the other hand, in the rough grinding process, a mixed mechanism of ductile and brittle grinding causes multi-layer damage and sub-surface cracks.

This basic understanding is an important step towards minimizing and subsequently removing the process-induced damage during mechanical grinding, and thus towards fabricating ultra-thin Si wafers.

[Figure Ultra-thin Si.jpg Damage models of PG-Si (a) and RG-Si (b).]

News from Holst Centre

Technology Report

ECG delineator algorithm extends wireless ECG patch

In the framework of Holst Centre, IMEC has further extended the functionality of its wireless ECG patch for cardiac monitoring. It added software that delineates the electrocardiography (ECG) signal locally on the patch node before sending the results over the air to the receiver. The algorithm achieves excellent results for sensitivity and predictivity, and covers a broad range of wave morphologies. The innovative ECG patch is intended to monitor single-lead ECG in daily-life conditions, opening new perspectives for cardiovascular disease management.

IMEC’s wireless ECG patch is a hybrid system combining electronic assembly on a flexible polyimide substrate and integration in textile. This enables flexibility in one dimension and stretchability in the other, which is required for optimal personal comfort. The patch features IMEC’s proprietary ultra-low-power biopotential ASIC, a commercial microcontroller and a 2.4GHz radio link. The patch can continuously monitor the patient’s heart at a sample rate of up to 1kHz. It sends the results directly to the receiver, or it can delineate the signals locally before sending them. Local delineation reduces the use of the radio, improving the autonomy of the patch. The current autonomy with local delineation is 10 days of continuous monitoring.

For local delineation, IMEC has now implemented a wavelet-based ECG delineator algorithm. The algorithm transforms the monitored ECG signal using discrete wavelet transform, and then performs a multi-scale search for the ECG waves. The delineator is able to identify P,Q, R, S, and T wave peaks and boundaries. Because the intervals and amplitudes of these waves contain most of the useful information of the ECG, this delineation will provide quick and useful information to the healthcare provider.

The QRS-wave search uses scales 21 to 23. It is based on modulus maximum lines, and the decision whether to consider a maximum modulus will be made immediately. The search will continue with adjacent slopes to delineate further QRS waves. The algorithm covers QRS, QR, RS, R, and QS wave morphologies. The search for P and T waves also uses scales 23 to 24. It follows the QRS delineation and covers the following morphologies: positive and negative, raising and falling waves for both P and T waves, and biphasic T waves.

The delineator on the ECG patch has been validated over all the records in the MIT-QT database. It achieves a 99.93% sensitivity and a 98.28% positive predictivity for QRS detection on 86,994 beats. For delineation over 3,623 beats, it reaches a 99.83% sensitivity and a 95.08% positive predictivity.

[Picture patch.JPG ECG patch for cardiac monitoring.]

News from IMEC’s (sub-)32nm research platform

Technology report

IMEC characterizes leakage current and anneal-induced defect creation in SiGe source/drain junctions

IMEC is studying embedded Si1-xGex source/drain regions as a way to create channel strain and thereby improve the hole mobility. One study, characterizing the impact of process parameters on the leakage current, shows the lowest leakage current to occur with post-epitaxy highly doped drain (HDD) implantation. A second study demonstrates the impact and applicability of millisecond annealing (MSA) for embedded SiGe S/D pMOS devices.

Strain engineering will be one of the enablers for future CMOS technology nodes, boosting the performance of both nMOS and pMOS transistors through the increase of the low-field mobility. In the case of p-channel transistors, using embedded SiGe source/drain (S/D) regions is a viable way to create the uniaxial compressive strain in the channel that will improve the hole mobility. But scaling this method to the 32nm and 22nm node will require shallower junctions. This can be compensated by increasing the Ge concentration in the S/D regions, resulting in a larger lattice parameter and thus in a larger compressive strain in the adjacent silicon channel.

IMEC has now investigated and characterized the impact of certain process parameters on the leakage current, which is one of the issues with embedded S/D processing. Embedded SiGe S/D junctions were examined with a varying Ge content between 20% and 35%. Also, the impact was studied of doing a HDD implantation before or after the selective epitaxial deposition of in-situ highly B-doped S/D layers. The lowest leakage current for a fixed Ge content was achieved with post-epitaxy HDD implantation. Moreover, the density of the leakage current becomes smaller for window sizes comparable with actual S/D junctions, which is favorable from a point of view of transistor OFF-state leakage.

A second concern is the optimization and control of the shallow implanted dopant profiles, which can strongly affect the series resistance and degrade the device performance. MSA, including rapid heating and cooling within 1 to 50 milliseconds, is one technique to activate the dopants in doped regions. IMEC examined if MSA is applicable to embedded SiGe S/D pMOS devices, and more in particular, it evaluated the impact of millisecond anneal in terms of defect creation and leakage current in the junctions. The study revealed an increase in motion of dislocations and dislocation density only for the splits that already showed some relaxation-induced defects before the laser annealing process. Moreover, the only case where the extended defects prior to the laser anneal were observed was with a post-epi ion implantation processed in the epilayers with 25% Ge, the highest Ge content used in this study. Finally, it can be concluded that the post-epi ion implantation conditions (size, depth and dose) play a key role in the compatibility of MSA with SiGe S/D pMOS devices, where high stress levels are required.

[picture SiGe SD.wmf SiGe source/drain regions.]


News from IMEC’s (sub-)32nm research platform

Technology report

IMEC helps set agenda for ESD protection of next-generation devices

At the 2008 International ESD Workshop, IMEC presented the keynote talk and two papers. In the keynote, IMEC listed challenges and solutions for electrostatic discharge (ESD) protection of future devices, given that further scaling will rapidly close the ESD design window. And the two IMEC papers discussed ESD in FinFET devices and in micro-electromechanical systems (MEMS).

With the continuing scaling of CMOS, ESD protection of the circuits becomes more and more of a challenge. A challenge that is corroborated by the introduction of new materials such as metal gates and high-k dielectrics, and new device architectures, such as multi-gate field effect transistors (e.g. FinFETs).

IMEC’s keynote talk held that, when classical scaling is maintained, the ESD design window will drastically decrease. The ESD design window is the window between the oxide breakdown voltage and the VDD voltage of the circuit. With shrinking gate dimensions, the oxide breakdown voltage is rapidly approaching the VDD, leaving little room for ESD protection. So traditional ESD protection solutions, such as the dual-diode approach, will no longer be an option and new techniques are needed.

On the same note, the workshop participants discussed the need to keep designing ESD protection for 2kV, the de-facto industry standard. Designing ESD protection for 2kV requires much overhead, needing extra space on the silicon, extra redesigns, and it takes a toll on the chip’s performance. But as the chip fabrication processes are all ESD-safe nowadays, circuits with ESD designed for 2kV do not have a lower rate of electrical overstress (EOS)/ESD failures than those designed for 0.5kV. An industry council with representatives of major semiconductor manufacturers and users is trying to come to a consensus on a new standard human body model (HBM) level.

IMEC’s first paper presented the results of testing the ESD performance of FinFETs. It is shown that reasonable ESD protection for FinFETs is possible. But the results also show a delicate sensitivity between the device layout and processing. For the first time, and through experiments and technology computer aided design (TCAD) simulations, it is possible to understand the effects of design options on the ESD robustness of FinFETs. And although the margins between success and failure are narrow, the results show that ESD protection should not be a showstopper for FinFET technology if the ESD protection is taken into account during the design and development. A second paper looked into the ESD protection of MEMS, showing the results of a case study on micromirrors. ESD sensitivity comes out as an inherent property of all actuated capacitive devices, and is thus a serious challenge in devices such as switches, resonators, or other types of air-gap devices.

[Picture designwindow With further scaling, the window between the oxide breakdown and the holding voltage closes.]


News from IMEC’s (sub-)32nm research platform

Technology report

IMEC reduces cost of double patterning lithography

IMEC, in collaboration with JSR Corporation, achieved 32nm lines and spaces with a double exposure/single etch process, effectively freezing the resist after the first exposure. This simplified process reduces the cost of double patterning, paving the way for an industrial take-up of double patterning for the 32nm technology node.

Double patterning will be the primary lithography candidate for the 32nm technology node. But when using two litho and two etch steps, this technique will be expensive and slow. Therefore, IMEC is developing alternative process flows that reduce the cost-of-ownership by eliminating the intermediate etch step and replacing it with a process step in the litho track.

One way to eliminate the extra etch step is through freezing the resist after the first exposure. With this technique, IMEC has demonstrated 32nm node logic patterning. The freezing material used to reach this result has been developed by JSR Corporation. It prevents the resist from expanding (i.e. critical dimension (CD) growth) or shrinking. And when the second resist layer is added, the two do not interact. Also, the freezing material is compatible with the lithography hardware.

The step of freezing the resist is done in the litho track. After exposing the first pattern, the resist is coated with the freezing material. Next, the wafer is baked to freeze the resist. Then the excess freezing material is removed using a developer. In the following step, a second resist layer is added and the second exposure is done. To prevent the second resist layer solvent from washing away the first resist, the freezing material changes the properties of the first resist layer so that it becomes non-soluble in the second resist layer.

This technique allowed printing 32nm dense lines using dipole illumination at 1.0NA. CD uniformity (CDU) for the 44nm half pitch lines was excellent (3s = 2.4nm). Moreover, 32nm node 2D logic cells as well as 32nm dense lines could be etched into poly. Lines resulting from the first and second lithography step cannot be distinguished, illustrating the good resolution obtained with this technique.

IMEC is now further developing this technique in close collaboration with the resist supplier. This work includes improvements of the process conditions, process window (PW), CDU, line-edge roughness (LER), line-end shortening (LES), overlay, defectivity, and etch performance.

[picture comparison.bmp (left) 32nm node 2D logic cells after litho-freezing-litho-etch. The lines from the two layers are perfectly merged on the stitching points. (right) The same cell patterned with litho-etch-litho-etch. The oxide hard mask has not been removed to show the lines obtained with the first litho step.]


News from IMEC’s Biomedical Electronics research

Technology report

IMEC develops proof-of-concept microfabricated probes for deep brain stimulation and recording

IMEC has developed a proof-of-concept microfabricated probe containing a 2D electrode array. This is a first step towards realizing a closed-loop system, where in-situ recordings are used to adjust the stimulation parameters. This development was done in collaboration with the Department of Experimental Neurosurgery of Leuven’s university hospital.

On the new probe, each electrode can be individually addressed for either recording or stimulating neural activity. The low-impedance electrodes (~200kΩ at 1kHz) with diameters ranging from 4 to 50µm ensure selective interaction with single neurons, thus improving the spatial resolution and targeting complex brain volumes. The probes were fabricated on Si/SiO2 wafers using gold or platinum as electrode material and parylene C as biocompatible insulation material.

In successful experiments, both recording and stimulation was demonstrated. Bandpass-filtered (500-5000Hz) signals showed low noise levels of around 20-30μVp-p with signal amplitudes up to 80μVp-p. Good recording was demonstrated by an offline analysis of the recorded material to extract the signals (spikes) originating from the neurons. And electrical stimulation could be demonstrated by sending monopolar current pulses into motor cortex neurons.

Increasingly, surgical therapies based on electrical deep brain stimulation (DBS) of specific brain regions are used for patients with movement and affective disorders that do not react well to other treatments. Examples are Parkinson’s disease, dystonia and essential tremor, and obsessive-compulsive disorders. Today, commercially available stimulators allow to finetune and program DBS parameters, including the stimulus amplitude, the duration, and the frequency band. However, the current technology allows only open-loop stimulation, which is not self-regulating and does not take into account the electrical or neurochemical activity of the brain. Instead, only the patient’s behavioral state is used as input to adjust the DBS parameters. This is not always efficient, and can give rise to stimulation-induced side-effects. Moreover, all the implantable electrodes in clinical use are handcrafted via precision machining, and are thus much larger and less precise than the new micromachined probe. As a result, only a limited number of stimulation sites with relatively large dimensions are currently used.

This work has been supported in part by the IWT-Vlaanderen under the SBO project Artificial Synapse (ASAP – 050151).

[picture Neuroprobes.emf]

News from IMEC’s SOLAR+ program

Technology report

New promising method to fabricate ultra-thin crystalline Si wafers for solar cells

IMEC is developing a new method to produce ~50μm thin crystalline silicon wafers for use in solar cells. The process involves mechanically initiating and propagating a crack parallel to the surface of a Si wafer. In this way, Si foils with an area of 25cm² and a thickness of 30-50μm have already been produced. The method makes use of industrially available tools (screen printer, belt furnace) and is potentially kerf-loss free.

Adding an ultra-thin wafer or foil of active silicon on top of a low-cost substrate is a promising solution to reduce the amount of high-grade silicon used in solar cells. IMEC is pursuing different paths to produce such foils of crystalline Si at an acceptable cost. One of the promising methods is a lift-off process that only requires the use of a screen printer and a belt furnace; no ion-implanted or porous layer is needed.

A metallic layer is screenprinted on top of a thick crystalline Si wafer, which is then annealed in a belt furnace at a high temperature. When the wafer cools, the mismatch of the thermal expansion coefficient between the metal and the silicon induces a stress field in the substrate. The stress field grows, initiating and propagating a crack in the silicon, close to and parallel with the surface. Next, the top layer of the silicon and the attached metal layer snap off from the parent substrate. The metal layer is removed from the silicon foil in a metal-etching solution, resulting in a clean and stress-free ultra-thin silicon foil. The substrate can be re-used to peel off further layers.

A 2D thermo-mechanical model was developed to understand the parameters influencing the crack trajectory. And the process was demonstrated on both single- and multi-crystalline silicon, as well as on Czrochalski (CZ) material with different orientations. IMEC already produced foils with an area of 25cm2 and a thickness of 30-50μm.

One of the resulting thin CZ foils was further processed into a solar cell using a heterojunction emitter process. The 1cm² cell reached an efficiency of 10.0%, without back-surface passivation or intentional surface texturing. These preliminary results indicate that the quality of the material is largely preserved during the lift-off process, in spite of the large stresses involved. IMEC expects to reach considerably higher efficiencies with added surface passivation and texturing.

[picture SR100F3.jpg Thermo-mechanical model of the lift-off process.]

[picture slimcut.tif Ultra-thin crystalline Si foil; this side shows the surface cut from the thicker substrate.]

Newsflash

IMEC board reports successful 2007

During its General Assembly, the IMEC board confirmed that 2007 was a successful year with excellent achievements, during which IMEC maintained its position as a world-leading nanoelectronics research institute. The board also looks confidently to 2008 and beyond.

The skills, devotion and hard work of the IMEC researchers led to many important results, evidenced by about 1,600 publications in prestigious journals and conference contributions, often in collaboration with universities in Flanders and abroad. The number of invited papers and lectures increased to 184, 32% more than in 2006. And in 2007, 106 patents were submitted. IMEC’s results were achieved by 1,572 people, a 5.5% increase compared to 2006. 35% of these were guest researchers and residents from the academic and industrial world.

2007 was also an excellent year from a financial viewpoint. IMEC’s total revenue (P&L) amounted to 244.5 million euro, of which 39.1 million euro were granted by the Flanders Government. In 2007, IMEC cooperated with many of the major semiconductor companies, giving it a large visibility and a good view on the future research needs.

In 2007, IMEC extended its programs to address the needs of all semiconductor players - from IDMs and foundries to fablite and fabless companies. Following the growing importance of memory technology, IMEC has brought its logic and memory research on equal footing. Among the new partners IMEC welcomed in 2007, two important additional memory players - Hynix and Elpida - joined the core (sub-)32nm program. For scaling-driven research, the focus is now on the sub-32nm technology. IMEC is tackling new research challenges, such as technology-aware design, and 3D design and architectures.

To maximize its efforts, IMEC has successfully merged all its scientific knowhow into one unit. This will ensure the leverage and knowledge-sharing that is needed to be successful in this research, where IMEC intends to combine ever more heterogeneous functionality on ever smaller footprints in ever more complex applications. Also, research was focused by giving a stronger weight to IMEC’s main application-oriented strategic drivers: nomadic embedded systems, wireless autonomous transducer systems, biomedical electronics, photovoltaics, and GaN power electronics.

[Figure IMEC Board Evolution of IMEC’s staff.]

News from IMEC’s Efficient Power program

Newsflash

IMEC and AIXTRON set important step towards low-cost GaN power devices

IMEC and AIXTRON, the world leader in metal-organic chemical-vapor deposition (MOCVD) equipment, have demonstrated the growth of high-quality and uniform AlGaN/GaN heterostructures on 200mm silicon wafers. This demonstration is a milestone towards fabricating low-cost GaN power devices for high-efficiency/high-power systems that overcome the limits imposed by silicon.

IMEC and AIXTRON deposited, for the first time ever, crack-free AlGaN/GaN structures on 200mm Si(111) wafers. The layers show a good crystalline quality – measured by high-resolution x-ray diffraction (HR-XRD) – and an excellent morphology and uniformity. The high-quality AlGaN and GaN layers were grown in AIXTRON’s application laboratory on the 300mm CRIUS metal-organic chemical-vapor-phase epitaxy (MOVPE) reactor.

The demonstration of GaN growth on 200mm Si wafers is an important step towards processing GaN devices on large Si wafers. There is a strong demand for GaN-based solid-state switching devices in the field of power conversion. However, bringing GaN devices to a level acceptable for most applications requires a drastic reduction in the cost of this technology. And that is only possible by processing on large-diameter Si wafers. 150mm, and next 200mm, are the minimum wafer sizes needed to fully leverage today’s silicon processing capabilities. The bow of the resulting wafers is still quite large, in the range of 100µm. But IMEC believes that an optimized buffer can reduce this bow drastically, enabling further processing. IMEC’s aim is to further develop this growth process and to qualify the wafers to be compatible with Si-CMOS processes.

Gallium nitride (GaN) has outstanding capabilities for high-power, low-noise, high-frequency, high-temperature operations, even in a harsh environment (radiation); it considerably extends the application field of solid-state devices. Due to the lack of commercially available GaN substrates, GaN heterostructures are nowadays grown mainly on sapphire and silicon carbide (SiC). Si is a very attractive alternative, being much cheaper than sapphire and SiC. Other benefits include the acceptable thermal conductivity of Si (half of that of SiC) and its availability in large quantities and large wafer sizes. But until now, Si wafers with (111) surface orientation were only available with a diameter up to 150mm. The 200mm wafers were custom-made by MEMC Electronic Materials, Inc. using the Czochralski growth (CZ) method. CZ wafers are ideally suited for switching applications with large breakdown voltages. For such devices, the performance is independent of the resistivity of the Si substrate.

Process details

For the AlGaN/GaN heterostructures, a standard layer stack was used that had already been successfully demonstrated on 100 and 150mm Si(111) substrates.
First an AlN layer was deposited onto the Si substrate, followed by an AlGaN buffer providing compressive stress in the 1µm GaN top layer. The stack was finished with a 20nm thin AlGaN (26% Al) layer and capped with a 2nm GaN layer. From in-situ measurements, IMEC extracted the thickness uniformity of the layers, showing a standard deviation well below 1% over the full 200mm wafers (5mm EE).

[Figure GaN.jpg Thickness uniformity map of a 1µm GaN layer deposited on 200mm Si(111) using an AlN/AlGaN buffer. The average thickness measured in-situ is 1008nm (σ = 0.5%) for the full wafer excluding a 5mm edge.]


News from IMEC’s Apollo program

Newsflash

IMEC’s >100Mbps SDR baseband chip functional


IMEC’s flexible-air-interface (FLAI) baseband platform for software-defined radios (SDR) is ready to support the next generation of high data rate mobile devices featuring, among others, 802.11n, 802.16e, and mobile TV. It also includes forward compatibility with the upcoming 3GPP-LTE communication standard. The system-on-chip (SoC) platform and its patented components with their programming environment will be licensed to industry for commercial product development as white-box intellectual property.

Within 2 weeks after receiving the first chip samples from the fab, IMEC researchers have proven that the silicon is fully functional. This result was based on 802.11a baseband code running in transmit and receive mode on the chip. In a next step, the baseband platform will be combined with IMEC’s flexible RF transceiver (SCALDIO) to demonstrate the multi-mode connectivity (i.e. switching from one standard to the other) of a fully operational SDR. IMEC’s SDR implementation will be followed by further research on next generations of SDR, gradually building up the capabilities of a cognitive radio. Industry partners are invited to join IMEC in this challenging research track.

The current FLAI platform incorporates two IMEC-proprietary ADRES (architecture for dynamically reconfigurable embedded systems) baseband processors, fully supported by a proprietary C-code compiler, three digital front-end tiles with a proprietary ASIP (application-specific integrated processor) to assure sync-detection, an ARM(TM)9 processor, and an optimized AMBA(TM) interconnect to link the SoC’s modules with on-chip memories. IMEC’s IP blocks come with reference platform control software and reference firmware for IEEE802.11n, 802.16e and 3GPP-LTE, as well as integration support.

The patented platform control and power management approach ensures that the SoC consumes only a few milliwatts in standby mode, yet is still capable of receiving an immediate burst from any supported wireless standard (reactive radio). And first measurements show that the actual power dissipation of the chip when transmitting or receiving data bursts in WLAN SISO 802.11a mode, is very close to state-of-the-art single mode solutions.

IMEC will have a booth at the SDR Forum Conference in October 2008 in Washington, giving live wireless demonstration of this technology.

NOTE

SDR baseband chip specifications

NOTE

IMEC has recently joined the SDR Forum ( www.sdrforum.org), endorsing the organization’s goal to advance the development and deployment of software-defined and cognitive radio technologies that enable flexible and adaptable architectures in advanced wireless systems. IMEC aspires to be a key player in the SDR field, which is gaining growing industry traction. In the last four years, IMEC has built a unique experience in SDR technology, which it will leverage to build next generation cognitive radios. These cognitive radios will have a dynamic and open access to the radio spectrum, motivated by the under-utilization of many licensed frequency bands.


[Picture bear.bmp IMEC's PCB containing the new baseband chip.]


News from Holst Centre

Newsflash

Holst Centre opens roll-to-roll research line for printed electronics

On June 19, Holst Centre officially inaugurated its roll-to-roll line for printed electronics. The current installation is a fully equipped pilot-production line for systems-in-foil printing, coating, drying and lamination. The next stage is the development of a complementary roll-to-roll deposition line for thin-film barriers on foil, currently in specification. Holst Centre also plans to build a dedicated roll-to-roll line for high-precision lamination.

Holst Centre will initially focus its activities on the roll-to-roll line on large-area printing and printed structures on flexible substrates. The main application driver is the development of device layouts and processes for flexible organic light-emitting diode (OLED) lighting and signage. Gradually, also other Holst Centre programs such as organic circuitry and lithography-on-foil will move towards roll-to-roll compatible processes.

Flexible electronics is an emerging market with a huge potential and with possible applications ranging from displays and lighting to smart packaging. While the technology is proven, there is a growing need for new manufacturing methods and technologies to support volume production.

Holst Centre collaborates with partners from the complete value-chain. These include materials suppliers (foils, active polymers, inks…), equipment manufacturers and product manufacturers, each having their own area of expertise. This type of collaboration allows defining open standards and smart interconnect technologies that will allow manufacturers to easily combine foils into end products.

[Picture RTR.0408.2766.jpg Roll-to-roll line for printed electronics.]


News from IMEC’s (sub-)32nm research platform

Newsflash

IMEC reports progress on simplified high-k/metal gate process for the 32nm node

At the 2008 VLSI Symposium, IMEC announced an improved performance for its planar CMOS using hafnium-based high-k dielectrics and tantalum-based metal gates for the 32nm CMOS node. The inverter delay advanced from 15ps to 10ps. IMEC also simplified its high-k/metal gate process by decreasing the number of process steps from 15 to 9.

High-performance (low-Vt) high-k/metal gate CMOS has recently been achieved by applying a thin dielectric cap between the gate dielectric and metal gate. Both gate-first and gate-last integration schemes have proven to be successful. While the gate-last scheme is now introduced in production for high-performance products, the gate-first option remains attractive for low-cost applications if its complexity can be reduced to the standard CMOS process flow. One of the possibilities for gate first is a dual-metal dual-dielectric process flow using mostly hard masks to pattern nMOS and pMOS regions selectively.

By applying conventional stress boosters to its gate-first dual-metal dual-dielectric high-k/metal gate CMOS, IMEC increased the performance of nMOS and pMOS transistors with 16% and 11% respectively. This results in an inverter delay improved from 15ps to 10ps. For the first time, the compatibility of conventional stress memorization techniques with high-k/metal gate has been demonstrated.

Also, IMEC has simplified the process complexity from dual-metal dual-dielectric to single-metal dual-dielectric by using soft-mask processes and wet removal chemistry. The process reduces the complexity by 40% or 6 steps compared to dual-metal dual-dielectric. It also allows simpler gate-etch profile control and it offers better prospects for scaling. And IMEC proved that the use of La and Dy capping layers does not result in reliability issues.

These results were obtained in collaboration with IMEC’s (sub-)32nm CMOS core partners including Infineon, Qimonda, Intel, Micron, NXP, Panasonic, Samsung, STMicroelectronics, Texas Instruments and TSMC, and IMEC’s key CMOS partners including Elpida and Hynix.

[Picture boundary.bmp SEM and x-TEM of nMOS/pMOS boundary in ring oscillator.]

[Picture delay.bmp Ring oscillator delay comparison of pSMDD versus FUSI/high-k reference.]

News from IMEC’s (sub-)32nm research platform

Newsflash

IMEC completes acceptance of ASML’s extreme ultraviolet Alpha Demo Tool

IMEC has successfully completed the integration and site acceptance tests of ASML’s extreme ultraviolet (EUV) Alpha Demo Tool (ADT) in its 300mm research facility. This paves the way for IMEC and its partners to research 22nm CMOS on the world’s most advanced lithography tool.

Since its shipment to IMEC in 2006, ASML’s full field EUV ADT has been gradually upgraded. After installation of the projection lens and first light with the Sn source (Philips Extreme UV), the optics have been further finetuned allowing the tool to meet the site acceptance specifications.

With the ADT now officially transferred to IMEC, IMEC and its partners can fully deploy the tool and examine solutions for the 22nm node. The EUV ADT will be used in IMEC’s industrial affiliation program to identify the key critical issues for EUV lithography and to propose solutions. This research will include (1) testing and benchmarking EUV resists using the full-field exposure tool; (2) integrating EUV lithography in a full CMOS process focusing on the 22nm technology node; (3) evaluating and improving the worldwide efforts on mask technology and (4) assessing the performance and stability of the EUV ADT.

Also, from now on, IMEC’s core partners will be offered the opportunity to use the ADT for their own research and for dedicated exposures, bringing in their own proprietary wafers and EUV reticles.

Although several critical issues still need to be solved, the acceptance of the ADT tool is an important milestone in the development of EUV technology, which is considered the technology for the 22nm half pitch insertion. In addition, IMEC demonstrated the patterning of the contact level of a 32nm SRAM cell, showing good prospects for EUV process integration. In 2010, ASML will install its EUV pre-production tool in IMEC’s 300mm facility.

[Figure [EUV.jpg] 32nm SRAM device after EUV ADT exposures with various doses and after oxide etch.]


News from IMEC’s Apollo program

Industry Link

Renesas collaborates with IMEC on reconfigurable RF transceivers

Renesas Technology Corp., one of the world's leading semiconductor system solutions providers for mobile, automotive and PC/AV (audio visual) markets, has entered into a strategic research collaboration with IMEC to perform research on 45nm RF transceivers targeting Gbit/s cognitive radios. To this end, Renesas has joined IMEC’s software-defined radio (SDR) front-end program. This research program includes reconfigurable RF solutions, high-speed/low-power analog-to-digital converters (ADCs) and new approaches to digitize future RF architectures.

Researchers from Renesas will reside at IMEC to closely collaborate with IMEC’s research team. In this way, they will build a fundamental understanding and develop robust solutions for Renesas future mobile electronics products.

Near term, IMEC’s SDR front-end program targets the development of a new-generation cost-, performance- and power-competitive reconfigurable radio in 45nm digital CMOS technology. This radio will have a programmable center frequency from 100MHz to 6GHz and a programmable bandwidth from 100kHz to 40MHz. It will cover all key communication standards, and have a merit comparable to state-of-the-art single-mode transceivers.

The research program builds on IMEC’s previous groundbreaking 130nm RF transceiver results (published at ISSCC 2007), which represented the world’s first prototype of a true SDR transceiver IC (SCALDIO). Also, further evolutions of IMEC’s record breaking ADCs (merit record by IMEC at ISSCC 2008 of 40Msamples/s, 9 bit, 54fJ/conversion step) will be developed within this collaboration.

This collaboration underlines the importance of IMEC’s recent results on SDR and ADCs, and stresses the value IMEC brings to its industry partners in this RF research program.

[Figure Renesas.jpg Renesas collaborates with IMEC on reconfigurable RF transceivers.]


News from Holst Centre

Industry Link

Singulus Mastering and Bekaert extend and expand participation in Holst Centre

Holst Centre has recently expanded its collaboration with two existing partners. For the young organization, this confirms that it has grown into a solid partner in research.

Bekaert, a world leader in advanced metal transformation and advanced materials and coatings, joined the two Holst Centre program lines on wireless autonomous transducer systems and system-in-foil in May 2006. After a successful two-year collaboration, the company decided to extend its commitment and strengthen its participation in several of the Holst Centre programs.

Singulus Mastering, market leader for optical disc production lines, enters into a full partnership in the Holst Centre lithography-on-foil program after an initial feasibility study that started in 2007. Erwin Meinders, Holst Centre Program Manager Lithography on Foil: “We are pleased to notice that our business model of consulting potential partners for the definition of a shared roadmap effectively leads to a win-win collaboration agreement that leaves room for various parties to join.”

Holst Centre was set up in 2005 by the renowned research centers IMEC (Belgium) and TNO (The Netherlands). From the start, it could count on considerable support from the government, academia and industry. During the pioneering phase, collaborations for shared research were signed with over 15 leading industrial partners. After two years, several of the initial contracts are evaluated in view of a continued collaboration.


NOTE about FutureFab

Download the latest edition of Future Fab International magazine at http://www.future-fab.com

Gilbert Declerck, CEO, IMEC and Lode Lauwers, Director Strategic Program Partnerships, IMEC participate in Future Fab’s editorial board, sharing their experience and industry outlook with the semiconductor community.

[picture FAB_logo_print_cmyk.tif ]

Courses

Bottom-up and top-down nanotechnology
November 12-14, 2008, IMEC, Leuven, Belgium
Organized by MTC and Marc Madou, University of California, Irvine, US

‘Bottom-up and top-down nanotechnology’ is a course for the broad audience of scientists and engineers from industry and academia with a keen interest in which technologies will supersede current electronics. The course should help academic and industry decision makers to make educated decisions on future R&D investments.

MEMS: Technology, design and applications
December 8-9, 2008, IMEC, Leuven, Belgium
        
This two-day training course focuses on the combination of NEMS/MEMS technology with standard CMOS. The emphasis will be on monolithic integration, i.e., processing of MEMS and CMOS on the same substrate. Also, close hybrid integration through transfer and wafer bonding techniques will be discusses and both processes will be compared. The course will deal with technology issues (manufacturing options and test) as well as application issues (products, markets). Design will be covered from a development point of view.
The course targets managers, project leaders, process engineers and technicians of standard CMOS wafer and MEMS fabs, equipment vendors and material suppliers.

Adhesion Science and Technology
December 8-9, 2008, IMEC, Leuven, Belgium

Adhesion plays an important role in many technologies and industries, namely automotive, thin films, optics, printing, medical, coatings, paint and so on. The need for understanding and controlling the factors affecting adhesion is quite patent. Also, the durability of the bond (on exposure to process chemicals, moisture, corrosives etc) is of grave concern and importance.
This two-day course provides up-to-date information on the factors affecting adhesion and introduces various ways to enhance adhesion in a host of situations. The target audience is research, development and manufacturing personnel who need a thorough knowledge of adhesion science and technology.

More information and a full overview of courses: www.imec.be/mtc

Events

EU PVSEC – 23rd European Photovoltaic Solar Energy Conference and Exhibition – Booth #3/B 8
September 1-5, 2008, Feria Valencia, Valencia, Spain

EU PVSEC is the most important international conference in the field of photovoltaics. The international collaboration, which the EU PVSEC facilitates, is essential in fostering a sustainable future for PV technology in the global energy system. During the exhibition, you can visit IMEC and discover recent progress made in bulk-Si solar cells (i-PERC and next generations), thin-film Si solar cells, organic solar cells, III-V solar cells and Ge thermophotovoltaic cell technology.

More information: www.photovoltaic-conference.com

UCPSS 2008 – 9th International Symposium on Ultra-Clean Processing of Semiconductor Surfaces
September 22-24, 2008, Bruges, Belgium

The Symposium on Ultra-Clean Processing of Semiconductor Surfaces is a biannual event that aims to increase the level of understanding on ultra-clean processing technology in all steps of the IC production. Paul Mertens, manager of IMEC’s program on contamination control, cleaning and surface preparation, will be the conference chairman.

More information: www.ucpss.org

5th International Symposium on Immersion Lithography Extensions
September 22-25, 2008, The Hague, The Netherlands

You are invited to join industry experts from around the world in presenting new and unique research results. Now in its fifth year, this symposium continues to focus on the progress in 193nm high-index immersion lithography, double patterning and other extensions to optical lithography, and to build consensus on how the industry will address emerging critical issues. IMEC, in cooperation with SEMATECH and Selete, will host this year’s Immersion Symposium.

More information: www.sematech.org/meetings or Email Contact

SEMICON Europa 2008 – Booth #2562
October 7-9, 2008, Stuttgart Trade Fair Centre, Stuttgart, Germany

Semicon Europe is an exciting environment where key participants in Europe’s complex and dynamic semiconductor market come together and focus on semiconductors, test, assembly and packaging, photovoltaic and MST/MEMS. Join IMEC and discover the latest achievements in solar cells, heterogeneous integration, 3D integration and scaling.

More info: www.semiconeuropa.org

ARRM 2008 – IMEC Annual Research Review Meeting 2008
The IMEC Research Business Forum
October 15-17, 2008, Radisson Sas Royal Hotel, Brussels, Belgium

Banner ARRM.jpg

Our society begs for innovative solutions to cope with problems such as climate change and sustainable energy, ageing, efficient and affordable healthcare, clean water supply, ubiquitous communication, and mobility. Semiconductor technologies and the convergence of technologies such as nanoelectronics and biotechnology – ‘the’ technology revolution of the 21st century – will create a virtually infinite umber of new appliances that will contribute to solutions for these social and environmental problems.

Stay up-to-date on evolutions, trends and breakthroughs in this changing and broadening semiconductor industry by attending the IMEC research business forum ARRM. With presentations by prominent industrial and IMEC speakers, the 2-day event is an ideal opportunity to get insight in the technology challenges and solutions for the coming years.

More information: www.arrm.be

2008 Software-Defined Radio Technical Conference and Product Exposition
October 26-30, 2008, Hyatt Regency Crystal City, Reagan Nat. Airport, Washington D.C., US

Reconfigurable radio technologies are moving into mainstream acceptance in a number of markets, reflecting the ability of these technologies to solve real problems in the wireless space. As a result, SDR 2.0, the next wave of innovation in both software-defined and cognitive radio technologies, will be driven more by market needs than by technical vision.
During this SDR Forum, IMEC will demonstrate its SDR solutions for mobile terminals in one live wireless demo setup and complementary design methodology demonstrators. The main features of this demo are flexibility in the RF transceiver, reprogrammability of the baseband platform and the unique low-power and high-performance behavior of the SDR solution.

More information: www.sdrforum.org

IMEC Executive SeminarI
November 11, 2008, Hotel New Otani, Tokyo, Japan

IMEC is organizing the ninth edition of its Executive Seminar in Tokyo, Japan, at which it will present its latest research results and industrial cooperation strategy to Executives and Technical Managers and Directors from Japanese semiconductor companies.

More information: www.imec.be/events

[Taiwan Kadertje]

[Events-Taiwan.tif]

3D Integration Workshop
A unique forum to debate on 3D integration issues, technological options, standards & conventions and roadmaps

November 13-14, 2008, Hsinchu, Taiwan

IC manufacturers and research groups are scrambling for a part of the 3D integration action. The first appliances with 3D chips are already available, with many more to come. But there are still a lot of questions surrounding 3D. Will 3D be limited to niche applications or will it become a widespread technology? Will 3D be cost-effective? What is the roadmap for 3D, and which of the many technical options will be used? How can 3D systems be tested? What are the requirements for the supply chain?
The aim of this 3D integration workshop is to discuss different views and initiate and stimulate the route towards standardizations in 3D.

Who should attend?

The whole 3D supply chain: IC manufacturers, the fabless community, tools and equipment suppliers, material suppliers, packaging and test houses and EDA suppliers.
Format:
Each session will start with a presentation of the consolidate view of major 3D players on key 3D technology topics, followed by an interactive discussion.

Organized by IMEC and IMEC Taiwan.        
Register now: www.imec.be/3Dworkshop