SynTest Extends Support for Additional IEEE Standards
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SynTest Extends Support for Additional IEEE Standards

                                                          “IEEE-1500 and IEEE-1149.6 Standards”

SAN JOSE, Calif., June 5, 2010 -- SynTest Technologies, Inc., a leading supplier of Design-for-Test (DFT) tools, announced full support for additional IEEE standards in the DFT product line. Support is now available for IEEE-1500 and IEEE-1149.6 standards.

ANSI/IEEE 1149.6-2003 - Standard for Boundary-Scan Testing of Advanced Digital Networks - defines extensions to IEEE Std 1149.1 to standardize the Boundary-Scan structures and methods required to ensure simple, robust, and minimally intrusive Boundary-Scan testing of advanced digital networks, especially those networks that are AC-coupled, differential, or both. This standard also specifies software and BSDL extensions to IEEE STD 1149.1, which are required to support new I/O test structures.

SynTest TurboBSDTM product used by the customers to insert boundary scan in their designs is compliant with IEEE-1149 standard.

IEEE STD 1500-2005 - IEEE Standard Testability Method for Embedded Core-based Integrated Circuits - defines a mechanism for the test of core designs within a system on chip (SoC). This mechanism constitutes hardware architecture and leverages the core test language (CTL) to facilitate communication between core designers and core integrators.

Support for the above standard can be used with SynTest TurboBIST-LogicTM and VirtualScanTM products. TurboBIST-Logic utilizes the powerful at-speed self-test technique with scan cores and a Multiple-Input Signature Register (MISR). VirtualScan™ is SynTest solution to combat a surge in test data volume and test cycle volume. With VirtualScan™ an extremely large number of short scan chains within the SOC can be virtually accessed from outside the chip with a limited number of pins assigned as scan pins. Both products use an array of powerful SynTest patents – staggered skewed-load and staggered double-capture – schemes for enhancing fault detection and minimizing number of patterns generated.

About SynTest
SynTest Technologies, Inc., established in 1990, develops IP for advanced design-for-test (DFT) and design-for-debug/diagnosis (DFD) applications and markets them throughout the world, to semiconductor companies, system houses and design service providers. The company has filed more than 38 US/PCT patents of which 17 have been issued and 1 allowed. The Company’s products improve an electronic design’s quality and reduce overall design and test costs. Various applications that use these IP (intellectual properties) include logic BIST, memory BIST, boundary-scan synthesis, Scan/ATPG with test compression, concurrent fault simulation, silicon debug and diagnosis. The company headquartered in Sunnyvale, California, has offices in Taiwan, Japan, Korea and China, and distributors in Europe and Asia including Israel. More information is available at

SynTest Technologies Inc. is headquartered at 505 South Pastoria Ave., Suite 101, Sunnyvale, California 94086, Phone: 408-720-9956, E-Mail: Email Contact

ATPG:       Automatic Test Pattern Generation
ATE:         Automatic Test Equipment
BIST:        Built-In Self-Test
DFT:         Design-for-Test
DFD:        Design-for-Debug/Diagnosis
IP:           Intellectual Property
TTM:        Time-to-Market


Ravi Apte,
Vice President, Marketing
408-720-9956 x 300