Silicon Integration Initiative (Si2) today announced the availability of a Common Power Format Relational Analyzer tool that will allow users of Si2’s CPF standard to analyze the design intent for a low-power design and examine the current state and relationships among the CPF data objects. The CPF Relational Analyzer is also useful as a training aid to learn/understand CPF, as an aid to ease the adoption process and as an analysis tool in the IC design process.
The CPF Relational Analyzer was developed by the in-house Si2 engineering staff, and is based upon the Low Power Coalition’s data model work. The Analyzer includes a relational database, and supports SQL-like queries on all the data objects and the many relationships between data objects. The Analyzer is built using Tcl/Tk scripts which interface directly to other EDA applications, thus allowing tighter integration into the design flow. The CPF Analyzer supports designs of any complexity or size, and includes an easy-to-use interactive GUI with extensive search and report features.
“The CPF Analyzer joins other useful adoption tools such as the CPF Parser, the CPF Pocket Guide, and the CPF Tutorial,” said Steve Schulz, president and CEO, Si2. “The goal of these tools is allow chip designers and developers to easily adopt CPF for rapid benefit to low-power designs and flows.”
The CPF Relational Analyzer is available to all members of the Low-Power Coalition. It will be demonstrated at the 12th Si2/OpenAccess+ Conference on April 16 in San Jose. Details on the conference are located here: http://www.si2.org/?page=934.
The CPF standard was approved and made publicly available in March of 2007, and since then has achieved wide acceptance in terms of EDA tool adoption, use in end-user tool flows, actual chip tape-outs and subsequent testimonials, and adoption into major foundry reference flows. CPF is supported not only by the Low Power Coalition, but also the Power Forward Initiative, http://www.powerforward.org.
About the Low Power Coalition (LPC)
The Low-Power Coalition (LPC) is delivering enhanced capabilities in low-power Integrated Circuit (IC) design flows in particular relating to specifications of low-power design intent, architectural tradeoffs, logical/physical implementation, design verification and testability. Member companies are: Advanced Micro Devices (NYSE: AMD), ARM (Nasdaq: ARMHY), Atrenta, Azuro, Cadence Design Systems (Nasdaq: CDNS), Calypto Design Systems, ChipVision Design Systems, Entasys, Freescale Semiconductor, IBM (NYSE: IBM), Intel (Nasdaq: INTC), LSI Logic (NYSE: LSI), NXP Semiconductors, Sequence Design, and Virage Logic (Nasdaq: VIRL). For further information on the Low Power Coalition, see http://www.si2.org/?page=726.
Si2 is an organization of industry-leading semiconductor, systems, EDA, and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time to market, reduce costs, and meet the challenges of sub-micron design. Si2 is uniquely positioned to enable collaboration through a strong implementation focus driven by its member companies. Si2 focuses on developing practical technology solutions to industry challenges. Si2 represents companies involved in all parts of the silicon supply chain throughout the world. www.si2.org
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