FishTail Tools Demonstrate Ability to Generate and Verify Timing Exceptions on Multi-Million Gate Design
Portland, Oregon, March 19, 2008 - FishTail Design Automation, Inc., the golden timing constraints company, today announced that Japan's Semiconductor Technology Academic Research Center (STARC) has released a new production flow for chip implementation using FishTail's technology for timing exception generation and verification. The STARCAD-CEL Version 2.0 flow includes the use of FishTail products Focus and Confirm to generate and verify false and multi-cycle paths on complex SoC designs.
STARC engineers conducted an exhaustive evaluation of the Focus and Confirm products from FishTail on a large suite of designs that ranged from simple test cases that exercised basic functionality to complex designs. The STARC evaluation represents one of the most comprehensive studies undertaken in the semiconductor industry to-date to assess the claims and abilities of different constraint generation and verification providers. FishTail's Focus and Confirm products demonstrated their ability to correctly generate and verify false and multi-cycle paths over all the design situations presented by the STARC test cases. Particularly noteworthy was the unique ability of FishTail products to both verify and generate multi-cycle paths on a ten million gate SoC with hundreds of clocks.
"I am enthusiastic in my endorsement of FishTail products for constraint generation and verification," said Nobuyuki Nishiguchi, vice president, general manager Development Dept.-1 of STARC. "The ability of FishTail products to provide correct results for both false and multi-cycle paths, while scaling to handle complex SoC designs is unmatched in the industry today."
"We are proud that the result of this detailed study at STARC shows that we continue to provide industry-leading solutions for constraint generation and verification," stated Ajay Daga, founder and CEO of FishTail. "FishTail's Confirm product is unique in its ability to verify whether timing exceptions are safe to apply across any and all circuit delays. Confirm is built on the most powerful sequential verification engine in the industry today - an engine that allows the tool to provide conclusive and correct answers for multi-cycle path definitions regardless of the size and clocking complexity of a design."
FishTail's Confirm product verifies the correctness of a constraint file. Confirm flags missing clocks, missing input/output delay constraints, conflicting case analysis settings and formally verifies false and multi-cycle path constraints. Confirm works with both RTL and netlist input. The use of Confirm to signoff on design constraints is a must to ensure first-pass silicon success.
About FishTail Design Automation
Founded in 2002, FishTail Design Automation has set its sights on tackling the difficult problem of precise constraints on chip timing - the area where the success or failure of a design is ultimately determined. The company's patented technology improves chip implementation by automatically generating and verifying exceptions to single-cycle clocking from RTL and netlist descriptions. FishTail is privately funded. For more information about FishTail, please visit the company's website at www.fishtail-da.com.
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Barbara Marker for FishTail